Xref: utzoo comp.lsi:1315 sci.electronics:17132 Path: utzoo!utgpu!news-server.csri.toronto.edu!bonnie.concordia.ca!thunder.mcrcim.mcgill.edu!snorkelwacker.mit.edu!hsdndev!rutgers!ucla-cs!oahu!frazier From: frazier@oahu.cs.ucla.edu (Greg Frazier) Newsgroups: comp.lsi,sci.electronics Subject: Re: Multi-port RAMs Message-ID: Date: 22 Jan 91 18:14:13 GMT References: <1991Jan22.005718.23369@mintaka.lcs.mit.edu> Sender: news@cs.ucla.edu (Mr. News) Organization: UCLA, Computer Science Department Lines: 30 Nntp-Posting-Host: oahu.cs.ucla.edu shers@masala.lcs.mit.edu (Alexander The Great Sherstinsky) writes: >Hello, >I am going to ask what might seem a stupid question, but here it goes anyway: >I am trying to build a new parallel computer as part of my thesis. At my >disposal are off-the-shelf components as well as the ability to build custom >chips (with MOSIS). Here is the problem: The architecture could really >benefit from having a large 5-port-read, 5-port-write RAM, all ports being >independent. Does such a beast exist? Or if I am going to design a custom >chip for it, how to do it without wasting too much silicon real estate? >Any response concerning this matter will be greatly appreciated. Jon's response was fairly accurate, but I think it danced around the issue that you are addressing. You're building a parallel computer. Since it is for a thesis, I assume that the architecture is unique in some way, and you have identified a need for multi- port RAM. Multi-port RAM is *very* expensive, as far as silicon goes. You would be much better off faking it, i.e. use single-port RAM's and find some way to multiplex them or put them into banks (as Jon basically said). -- Greg Frazier frazier@CS.UCLA.EDU !{ucbvax,rutgers}!ucla-cs!frazier