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From: sam2y@spot.cs.virginia.edu (Steven A. Moyer)
Newsgroups: comp.sys.intel
Subject: DRAM controllers
Message-ID: <1991Jan15.161737@spot.cs.virginia.edu>
Date: 15 Jan 91 21:17:37 GMT
Sender: news@murdoch.acc.Virginia.EDU
Reply-To: sam2y@spot.cs.virginia.edu (Steven A. Moyer)
Distribution: usa
Organization: University of Virginia
Lines: 25

I have a question concerning DRAM controllers that maybe someone can help
me with.  In particular, DRAM controllers for page-mode DRAMs.

During fast page reads RAS is held low while CAS is toggled as column
addresses are applied.  When an access requires that a new row be read
from the DRAM array, the DRAM controller state machine (at least the
one that I am working with) enters a precharge state which requires 
several CPU clock cycles.

My question is, what occurs during this precharge state?

Since the state after the precharge state is the idle state, it doesn't
appear to be part of the row access.  My guess is that maybe writes only
affect the buffer which holds the most recently read row, and that during
precharge this buffer is written back.  I would like to know for sure.

Thanks for any help.
--

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| Steven Moyer                   |       THIS SPACE FOR RENT         |
| University of Virginia         |                                   |
|                                | "Just a rebel without a clue..."  |
| E-mail: sam2y@virginia.edu     |                - The Replacements |
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