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From: vjs@calcite.UUCP (Vernon Schryver)
Newsgroups: comp.unix.sysv386
Subject: Re: binary Mach distribution for 386
Message-ID: <104@calcite.UUCP>
Date: 18 Jan 91 05:40:01 GMT
References: <13963@uswat.UUCP> <1991Jan4.140341.11874@granite.cr.bull.com> <1991Jan15.182524.14868@scuzzy.in-berlin.de>
Organization: Rhyolite Software, Mountain View, CA
Lines: 29

In article <1991Jan15.182524.14868@scuzzy.in-berlin.de>, src@scuzzy.in-berlin.de (Heiko Blume) writes:
>  ...
> that's why i mentioned the intelligent peripherals. it's necessary
> to offload the network code to the interface anyway. for example, with host
> based tcp/ip over 100Mbit FDDI you get about 20Mbit/s max throughput.
> if you use the FDDI- and TCP/IP-chips you get about 70Mbit/s.
> i think that clearly shows the way to go.


I've kept my daytime employer convinced of several contrary statements.
One is that my code does much more than 20Mbit/sec TCP/IP/FDDI while doing
no more than the link layer on the board, and that this is not an
accident.  Another is that the fact that smarter ethernet boards are 
slower on this series of systems is not due to our group's stupidity.

There was an FDDI board vendor claimed 80Mbit/sec at InterOP 89.  More
recent, real benchmarks offered to try to sell us the same board were
closer to 15 Mbit.  The highest honest TCP/IP/FDDI numbers I have heard in
the halls around X3T9.5 meetings and via industry gossip of "secret"
projects are ~40Mbit/sec.  (Please infer nothing about my forthcoming
efforts.)  I will be in your debt if you point out announcements of numbers
larger than 30Mbit.  80Mbit is easy if you continual blast the same
packets.  TCP/IP delivered to application processes is harder.

I do not know of any "TCP/IP chips", although I know about PEI and XTP.
To what are you referring?


Vernon Schryver,   vjs@calcite.uucp