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From: tomb@hplsla.HP.COM (Tom Bruhns)
Newsgroups: sci.electronics
Subject: Re: The 555
Message-ID: <5170100@hplsla.HP.COM>
Date: 15 Jan 91 21:56:09 GMT
References: <10014@as0c.sei.cmu.edu>
Organization: HP Lake Stevens, WA
Lines: 26

rsd@sei.cmu.edu (Richard S D'Ippolito) writes:

>If my memory is serving me correctly, I seem to recall (from 10 or more
>years back!) that there is a fundamental design flaw with the 555 timer
>chip, in that there are certain operating conditions and external part
>values which could cause part of the chip circuitry to latch up (like a
>thyristor), a condition requiring power removal to reset, making the 555
>definitely unsuitable for a watchdog design.  My further recollection is
>that the flaw was publically aired in some of the professional/trade
>magazines, such as EDN, causing no little excitement for the original
>manufacturer.

I don't recall that, and I've never had that severe a problem with a 555
myself, but I recall some time ago having a problem with them in the
nature of a 'latchup' condition.  It had to do with starting a standard
555 oscillator.  As I recall, Threshold and Trigger were tied together and
to Discharge (though there may have been a resistor to Discharge -- long
time ago ;-), and a rather high-value resistor went off to a + voltage
from there.  Capacitor from Thr/Trig to gnd.  Bypass on pins 5 and 8 like
a good boy.  Problem was that the voltage on the trigger input was low
enough to cause trigger to not trigger; if I raised it a few millivolts,
it would take off and run.  Hope this tangent helps some.  Don't recall
if it was just one mfgr or several, but it was repeatable pretty well at
room temp from one chip to the next.  The resistor to the + voltage was
small enough to supply appropriate bias currents.  (Reflecting on it,
there probably _was_ an R off to Discharge from Trig/Thresh...)