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From: mash@mips.COM (John Mashey)
Newsgroups: comp.arch
Subject: Re: Page size and linkers (was: Re: SunMMU history)
Message-ID: <45242@mips.mips.COM>
Date: 25 Jan 91 20:10:42 GMT
References: <1991Jan19.133914.23871@bellcore.bellcore.com> <PCG.91Jan20191955@teacho.cs.aber.ac.uk> <3981@skye.ed.ac.uk> <MOSS.91Jan21172107@ibis.cs.umass.edu>
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Reply-To: mash@mips.COM (John Mashey)
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In article <MOSS.91Jan21172107@ibis.cs.umass.edu> moss@cs.umass.edu writes:
>MIPS systems have a tool that reorganizes code for better *cache* behavior.
>The same idea would presumably work for paging (and TLB) stress reduction ...

Yes,  although as it stands, the tool only does it for code, not data;
for many programs, code impact on paging and TLB is much less than
data impacts .... or in some cases, the code impact is horrible, but
there's nothing in the world that can be done about it except to have
huge caches, and even better, fast cache refill.  (Consider the kind of
program that's >200MB of code, much of it in a giant single loop,
leading to a high I-cache miss rate.)
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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