Path: utzoo!attcan!uunet!cs.utexas.edu!sun-barr!newstop!exodus!cortex.Eng.Sun.COM!rtrauben
From: rtrauben@cortex.Eng.Sun.COM (Richard Trauben)
Newsgroups: comp.arch
Subject: Re: How about CACHE based registers, was: more registers for ix86
Message-ID: <5820@exodus.Eng.Sun.COM>
Date: 12 Jan 91 16:14:08 GMT
References: <1991Jan6.014925.10935@zoo.toronto.edu> <47789@apple.Apple.COM> <4300@skye.cs.ed.ac.uk> <47986@apple.Apple.COM>
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Organization: Sun Microsystems, Mt. View, Ca.
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>It is not clear to me that cache based register are a win. They might be,
>but it not clear, and I have heard counterexamples.
>The ATT CRISP uses essentially a multi-ported cache for their 'registers'

The initial CRISP design made no attempt to keep the stack cache consistent
with the memory hierarchy. Processes on different CRISP processors in an 
MP machine that shared a stack were asking for 
subsequent implementations revised this policy.if 
-richard