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From: lindsay@gandalf.cs.cmu.edu (Donald Lindsay)
Newsgroups: comp.arch
Subject: Tomasulo
Summary: CAM-addressed registers??
Message-ID: <11705@pt.cs.cmu.edu>
Date: 29 Jan 91 00:13:59 GMT
References: <1991Jan23.154727.26972@mozart.amd.com>
Organization: Carnegie Mellon Robotics Institute, School of CS
Lines: 19


In article <1991Jan23.154727.26972@mozart.amd.com> 
	tim@amd.com (Tim Olson) writes:
>Register file access is not on the most critical path in the Am29000
>(and we have 192 3-ported registers!).  Usually cache lookups and TLB
>matching tend to be more critical, because they involve an immediate
>comparison of tags after the access, and the arrays are usually larger
>than register file arrays.

Does this mean that a machine with Tomasulo-style tag matching would
have no cycle time penalty?  How sensitive would that be to the tag
width, when there are, say, 50 or 80 destinations?

[I am referring to a machine where tagged values are broadcast over
an internal bus, and destinations select themselves via tag matching.
The 360/91 FPU used this in place of traditional register address
decoders.]
-- 
Don		D.C.Lindsay .. temporarily at Carnegie Mellon Robotics