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From: davidb@brac.inmos.co.uk (David Boreham)
Newsgroups: comp.arch
Subject: Re: Real Time/Cache
Message-ID: <14118@ganymede.inmos.co.uk>
Date: 29 Jan 91 11:43:27 GMT
References: <11190@pt.cs.cmu.edu> <90331.001007DXB132@psuvm.psu.edu> <11228@pt.cs.cmu.edu> <17999@cbmvax.commodore.com>
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In article <17999@cbmvax.commodore.com> jesup@cbmvax.commodore.com (Randell Jesup) writes:
>	Instead of making on-chip cache, for real-time work on-chip FAST
>memory may well be better, especially if it's managed properly.  The new
>AT&T DSP uses this sort of memory (the 3210 has 2K of on-chip multi-port
>SRAM).
>
>	The cache does nothing for you in a realtime application since you
>have to assume worst-case anyways (well, not nothing, but not far from it -
>non-realtime tasks on the same machine might get an advantage).

Old hat. All our processors have had on-chip 4K SRAM for years.

Why not make a processor which has the facility to use the on-chip
SRAM as either a cache, or SRAM, or half-in-half ? 

David Boreham, INMOS Limited | mail(uk): davidb@inmos.co.uk or ukc!inmos!davidb
Bristol,  England            |     (us): uunet!inmos.com!davidb
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