Path: utzoo!utgpu!watserv1!maytag!xenitec!zswamp!root
From: root@zswamp.fidonet.org (Geoffrey Welsh)
Newsgroups: comp.dcom.modems
Subject: Re: Abstracts of papers for upcoming V.fast Meeting
Message-ID: <6677.27A3B01E@zswamp.fidonet.org>
Date: Sun, 27 Jan 91 12:40:11 EST
Organization: Izot's Swamp BBS - Kitchener, Ontario

 >From: tnixon@hayes.uucp

 >The best choice will probably be EIA-530.  This uses the 
 >same 25- or 26-pin connector as EIA-232, but uses EIA-422 (balanced) 
 >circuits for signals that change quickly (data, clocks) and EIA-423 
 >(unbalanced) circuits for signals that don't change as often 
 >(DTR, DCD, etc.)

   Do we really need a mongrel serial design?  Is the cost of going whole-hog 
balanced that high that we can't afford the consistency?

 >One example of a device which can take the load off the CPU 
 >for high-speed transfer is the Hayes Enhanced Serial Port (ESP).  
 >It has two 16550AFNs on it, plus an 8031 microcontroller.  Both 
 >transmit and receive have 1K-byte FIFOs, and the 8031 supports direct 
 >DMA transfers to/from main memory.

   Ah, I was wondering what those things were, thanks for the info.

 >There are similar buffered devices from 
 >other companies, but most of them don't preserve backward 
 >compatibility with existing comm software (which ESP does).

   Then I don't suppose that the ESP uses the 16550's DMA mode?
 

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