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From: paw@pawsun.ece.uc.edu (Philip A. Wilsey)
Newsgroups: comp.lang.vhdl
Subject: vhdl input/output....
Keywords: vhdl
Message-ID: <7306@uceng.UC.EDU>
Date: 24 Jan 91 23:01:01 GMT
Sender: news@uceng.UC.EDU
Reply-To: paw@uceng.uc.edu
Followup-To: paw@uceng.uc.edu
Organization: University of Cincinnati
Lines: 62


I have been studying VHDL and have turned to file I/O.  The LRM is not
particularly helpful in this matter and so I have a coupe of
questions.  The context of my questions will be where a common
architecture exists with two process statements.  Assume that each
process statement contains a I/O request to the same file.  For
example, consider the following VHDL code fragment: 

architecture demo_arch of demo is

File InputFile : STRING is in "HostFileName";
variable L : Line;

P1: process 
begin
readline(InputFile, L);
....

end process P1;

P2: process
begin
readline(InputFile, L);
...

end process P2;

In additional, assume that the processes will be active at the exact
same times and, therefore, that the readlines will be executed in the
same simulation cycle.

What happens?  More precisely, assume that the VHDL simulator is built
on a parallel processing system and that the two processes will be
executing on distinct processors.  Do these processes receive
alternate records from the input file?  Furthermore, if there are an
odd number of records (lines) in the input file, then only one of
these processes should process the last line.  However, the test
"endfile" and subsequent "readline" are not atomic actions and
therefore, it is possible for each process to receive false on the
endfile before actually reading the file (and hence one of them would
read past the end).   

Secondly, what happens on output?

Finally, how is a line defined.  Consider a file of type character.
Is the newline character read/writable?  If so, then what actually
defines the line?

I apologize for the length of this query, but I am really confused
about file types and I/O.  Any clarification would be immensely
helpful. 

Thanks in advance.

-- 

Philip A. Wilsey
Computer Architecture Design Laboratory
Dept. of Electrical & Computer Engineering
Cincinnati, OH  45221-0030
(513) 556-4779
paw@uceng.uc.edu