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From: phil@brahms.amd.com (Phil Ngai)
Newsgroups: comp.sys.ibm.pc.misc
Subject: Re: Paged vs. Paged-Interleaved Memory
Message-ID: <1991Jan25.201412.26354@amd.com>
Date: 25 Jan 91 20:14:12 GMT
References: <38421@cup.portal.com>
Sender: usenet@amd.com (NNTP Posting)
Organization: Advanced Micro Devices, Inc; Sunnyvale, CA
Lines: 17

In article <38421@cup.portal.com> mmm@cup.portal.com (Mark Robert Thorson) writes:
|I'm trying to figure out the value of paged vs. paged-interleaved memory
|in PC's with multiple banks.  These are both techniques for keeping a
|DRAM page active in each bank when you have more than one bank of DRAM.

One issue you left out is access time. If you have page mode 100 nS DRAM,
your minimum cycle time is about 80 nS or so. (50 nS access time, plus
5 ns rise/fall time, 10 ns setup time, 10 prop time, etc) This is hard
to take to 25 MHz. (not impossible, but challenging)

If you do page mode and interleaving, then you can reduce your minimum
cycle time.

--
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