Path: utzoo!utgpu!news-server.csri.toronto.edu!bonnie.concordia.ca!thunder.mcrcim.mcgill.edu!snorkelwacker.mit.edu!usc!wuarchive!udel!rochester!pt.cs.cmu.edu!a.gp.cs.cmu.edu!koopman
From: koopman@a.gp.cs.cmu.edu (Philip Koopman)
Newsgroups: comp.lang.forth
Subject: Re: TOS in a CPU register
Summary: TOS in register usually good
Message-ID: <11801@pt.cs.cmu.edu>
Date: 6 Feb 91 02:54:45 GMT
References: <1134@pcsbst.pcs.com>
Organization: Carnegie-Mellon University, CS/RI
Lines: 19

In article <1134@pcsbst.pcs.com>, hgw@rht32.pcs.com (h.-g. willers) writes:
> Given an indirect threaded FORTH for a RISC-procesor (R3000 or i860).
> What is the best implementation (concerning speed) for Top-of-Stack,
> ...
> Having too many stack items in CPU registers generates much shuffling
> of data for some stack operations. Which implementation should be
> chosen?

I compared actual implementations on an 80286, and found that TOS in
register was 10% to 15% faster than TOS not in a register.
I expect this will be broadly true for most other register-based CPUs
(i.e., not 1%, and not 30%, but probably something in between).
Having more than 1 stack element in registers led to too much shuffling
to be worthwhile.

  Phil Koopman                koopman@greyhound.ece.cmu.edu   Arpanet
  2525A Wexford Run Rd.
  Wexford, PA  15090
*** this space for rent ***