Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!samsung!sol.ctr.columbia.edu!emory!hubcap!Steven From: zenith@ensmp.fr (Steven Ericsson Zenith) Newsgroups: comp.parallel Subject: iWARP and neural nets Message-ID: <12929@hubcap.clemson.edu> Date: 5 Feb 91 16:38:12 GMT Sender: fpst@hubcap.clemson.edu Lines: 29 Approved: parallel@hubcap.clemson.edu In-Reply-To: Steve Stevenson's message of Tue, 5 Feb 91 08:00:25 -0500 <9102051300.AA06299@hubcap.clemson.edu> yarri@rainier.eng.ohio-state.edu (Douglas Yarrington) says about iWARP: I'm interested in seeing how this type of processor encroaches on the realm of fine-grained neural networks, so I'd like to find some references, preferably recent, on the hardware structure. Could someone point me in the right direction please. I'd say this type of processor does not at all encroache on the realm of fine-grained neural networks, for pretty much the same reason the transputer doesn't. When you talk about Neural Net silicon you need something closer to a memory device, not a CPU. Look out "Analog VLSI and Neural Systems" by Carver Mead, published by Addison-Wesley. 1989 And checkout Igor Aleksander's excellent contribution "Myths and Realities about Neural Computing Architectures" (the first chapter) to: "Parallel Processing and Artificial Intelligence" Eds. Mike Reeve and Steven Ericsson Zenith published by John Wiley. 1989. Steven -- Steven Ericsson Zenith * Email: zenith@ensmp.fr * Fax:(1)64.69.47.09 | Francais:(1)64.69.47.08 | Office:(1)64.69.48.52 Center for Research in Computer Science - Centre de Recherche en Informatique CRI - Ecole Nationale Superieure des Mines de Paris 35 rue Saint-Honore 77305 Fontainebleau France