Path: utzoo!censor!geac!torsqnt!lethe!yunexus!ists!helios.physics.utoronto.ca!news-server.csri.toronto.edu!bonnie.concordia.ca!uunet!mcsun!ukc!cam-cl!news
From: nbvs@cl.cam.ac.uk (Nicko van Someren)
Newsgroups: comp.sys.acorn,eunet.micro.acorn
Subject: Re: RAM speed
Message-ID: <1991Feb3.205155.23563@cl.cam.ac.uk>
Date: 3 Feb 91 20:51:55 GMT
References: <2268@cybaswan.UUCP> <1991Feb3.051225.26088@alzabo.uucp>
Reply-To: nbvs@cl.cam.ac.uk (Nicko van Someren)
Organization: U of Cambridge Comp Lab, UK
Lines: 16

You can indeed crank up the clock speed to MEMC but this has some nasty
side effects.  The main problem stems from the fact that doing just that will
crank up the clock to IOC and this all your times will run fast, you hard
disc controler's phase-locked loops will run fast and lots of others besides.

What you realy need to do is to run the MEMC and IOC at different speeds and
have a small circiut to fix the signals inbetween.  This is what the 540 does.
I have built a circuit to do this but it is realy nasty, does not always work
reliably and needs tracks on the PCB cut before it can be fitted.
In my experiance it is not worth the bother.


+-----------------------------------------------------------------------------+
| Nicko van Someren, nbvs@cl.cam.ac.uk, (44) 223 358707 or (44) 860 498903    |
|       "Go and buy an Aleph One ARM3 card and stop whining!!!"               |
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