Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sdd.hp.com!news.cs.indiana.edu!news.nd.edu!mentor.cc.purdue.edu!purdue!haven!adm!smoke!gwyn
From: gwyn@smoke.brl.mil (Doug Gwyn)
Newsgroups: comp.sys.apple2
Subject: Re: ASIC-65816 News
Message-ID: <15043@smoke.brl.mil>
Date: 1 Feb 91 18:29:05 GMT
References: <9242@uwm.edu> <1991Jan31.065813.25807@nntp-server.caltech.edu> <9261@uwm.edu>
Organization: U.S. Army Ballistic Research Laboratory, APG, MD.
Lines: 31

In article <9261@uwm.edu> mcgu5464@csd4.csd.uwm.edu (Ronald J Mcguire) writes:
>But isn't a faster CPU in effect an accellerator? Or how do they do it
>now? Sorry about the dumb question, but I really don't understand!

The "CPU" in question is a single integrated circuit ("chip") that can
be used as the nucleus of a computing system but requires substantial
supporting circuitry, for example a master clock that provides the
timing "ticks" in units of which the rest of the logic circuitry
operates.  While the rumored ASIC chip would have the potential of
operating correctly when clocked at speeds much greater than the 2.8MHz
used on the Apple IIGS motherboard, merely replacing the CPU chip on
the motherboard with one capable of faster clocking would not improve
the throughput of the computer system so long as the same 2.8MHz clock
continued to be used.  There are various technical reasons why the
clock speed on the IIGS motherboard itself cannot be increased.  Thus
accelerator add-ons like AE's TransWarp/GS (which connects to both an
Apple II bus slot and the motherboard CPU socket) provide their own
fast clock and other associated support circuitry.  Because they have
to cooperate with the circuitry still on the IIGS motherboard, there
is some fairly tricky coordination required in the design of such
accelerators.  Because Apple IIGS RAM typically fails if clocked much
faster than 2.8MHz, increased CPU speed alone would not be much of a
gain, due to having to wait for the rest of the Apple IIGS to operate.
Therefore, accelerator add-ons normally provide some fast RAM "cache"
memory so that a good percentage of all memory accesses can be
satisfied more quickly than would be the case if direct access to the
standard IIGS RAM were required.  Some IIGS operations simply require
that the accelerator revert to normal IIGS speeds, for example 1MHz
when accessing Disk II controller cards (whose firmware performs
critical disk read/write timing using the "known" times taken for
certain instruction sequences on the original 1MHz Apple II).