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From: toddpw@nntp-server.caltech.edu (Todd P. Whitesel)
Newsgroups: comp.sys.apple2
Subject: Re: ASIC-65816 News
Message-ID: <1991Feb2.033541.23134@nntp-server.caltech.edu>
Date: 2 Feb 91 03:35:41 GMT
References: <5542@husc6.harvard.edu> <5544@husc6.harvard.edu>
Organization: California Institute of Technology, Pasadena
Lines: 22

swiers@plains.NoDak.edu (Mike Swiers ) writes:

>Seems to me, you take something like 1/25Mhz and that gives you the speed of
>the chips you need in ns....I think you have to account for some overheard
>in there as well......

That's more or less how STATIC CACHE ram speeds are determined.

The SIMMs everyone is buying for $40 contain memories of a totally different
nature -- they are much larger than an accelerator's cache needs to be, and
are slower than they seem because 80 ns is only a 'best case' access time
(which you only get for consecutive accesses to the same 'page' of the chip;
a DRAM page is usually the square root of the memory size, so 64K drams have
a 256-location page, 256K drams have a 512-location page, and so on).

DRAMs are used for main memory because they are big & cheap. Caches use static
rams (which have a constant and usually short access time, depending on how
much you want to pay) in order to avoid waiting for the DRAMs 90% of the time,
and it works rather well.

Todd Whitesel
toddpw @ tybalt.caltech.edu