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From: rhyde@ucrmath.ucr.edu (randy hyde)
Newsgroups: comp.sys.apple2
Subject: Re: ASIC-65816 News
Message-ID: <11642@ucrmath.ucr.edu>
Date: 2 Feb 91 07:02:32 GMT
References: <5544@husc6.harvard.edu> <1991Feb1.174430.7516@dartvax.dartmouth.edu> <7890@plains.NoDak.edu>
Organization: University of California, Riverside
Lines: 15

>>>>>>
Seems to me, you take something like 1/25Mhz and that gives you the speed of
the chips you need in ns....I think you have to account for some overheard
in there as well......
<<<<<

Actually, the 65xxx requires memory accesses to take place in 1/2 a clock
cycle, so you would need somewhat less (because the clock is asymmetrical)
that 1/50Mhz (20ns).  You are right about some additional overhead.  The
decoding, address and data buffers, and stray capacitance all take away
nanoseconds.  You'd probably need RAM faster than 5ns to work on a 25Mhz
65c816 without wait states.  I have seen TTL compatible 7ns RAM, any faster
than this and you've got to go to incompatible logic families.  Of course,
you'd also have to be filthy rich to afford any of this stuff.
*** Randy Hyde