Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!wuarchive!sdd.hp.com!caen!uwm.edu!ogicse!plains!swiers
From: swiers@plains.NoDak.edu (Mike Swiers )
Newsgroups: comp.sys.apple2
Subject: Re: ASIC-65816 News
Message-ID: <7897@plains.NoDak.edu>
Date: 2 Feb 91 08:37:41 GMT
References: <1991Feb1.174430.7516@dartvax.dartmouth.edu> <7890@plains.NoDak.edu> <11642@ucrmath.ucr.edu>
Organization: North Dakota State University, Fargo
Lines: 17

In article <11642@ucrmath.ucr.edu> rhyde@ucrmath.ucr.edu (randy hyde) writes:
>
+>Actually, the 65xxx requires memory accesses to take place in 1/2 a clock
+>cycle, so you would need somewhat less (because the clock is asymmetrical)
+>that 1/50Mhz (20ns).  You are right about some additional overhead.  The
+>decoding, address and data buffers, and stray capacitance all take away
+>nanoseconds.  You'd probably need RAM faster than 5ns to work on a 25Mhz
+>65c816 without wait states.  I have seen TTL compatible 7ns RAM, any faster
+>than this and you've got to go to incompatible logic families.  Of course,
+>you'd also have to be filthy rich to afford any of this stuff.
>*** Randy Hyde

How much are we talking here?  I just can't believe 32K of RAM, no matter how
fast, is that expensive.  I mean, I'd pay $500 for a 25Mhz accelerator.  Is
that a lot?

Mike