Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!samsung!munnari.oz.au!uhccux!waikato.ac.nz!aukuni.ac.nz!qzhe1 From: qzhe1@cs.aukuni.ac.nz (Qun Zheng ) Newsgroups: comp.sys.mips Subject: Re: What are the new features in MIPS-II instruction set? Message-ID: Date: 5 Feb 91 05:00:55 GMT References: Sender: news@ccu1.aukuni.ac.nz (News Owner) Organization: University of Auckland, New Zealand. Lines: 19 MIPS-II does not use delayed-load. Why? Most MIPS instructions are RRR/RRI type. So how is MEM stage justified? I know the address calculation is done in EX stage. But this calculation can be done is one instruction and then use another instruction to do indirect access. So EX stage uses ALU for ALU operations and accesses memory for load/store. Note that RISC never encourage people to program in assembly level, so not much in- convenience here. Maybe because lots of load/stores used in programs? It does not have to any performence gain by changing the pipeline. But there must be some important factors in the design. Mind you informative/intelligent netters give me some insight. Thanks in advance. Chuck Q ZHENG Dept CompSci Auckland University New Zealand