Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sdd.hp.com!think.com!linus!linus!chance.mitre.org!tomg From: tomg@chance.mitre.org (Tom Gerasch) Newsgroups: comp.sys.sequent Subject: instruction cache Keywords: bus use, instruction cache, Intel segments Message-ID: <1991Feb1.153112.14717@linus.mitre.org> Date: 1 Feb 91 15:31:12 GMT Sender: tomg@mitre.org Distribution: comp.sys.sequent Organization: The MITRE Corporation, McLean, VA Lines: 35 Nntp-Posting-Host: chance.mitre.org I need some information about instruction cacheing on the Symmetry. I have been told that the 128KB cache that each processor has on the Symmetry is used only for data, that instructions are not cached. I would think that the movement of instructions over the bus when one has a medium to large Symmetry configuration would tend to saturate the bus. I know that the Intel 386 processor has a 16 byte on-chip instruction queue, but some simple back-of-the-envelope calculations seem to indicate that with 16 processors, say, and assuming that the instructions executed are 2 to 4 bytes long and take 4 to 8 clocks, on the average (I know, not real arithmetic computation), that we would be getting near 50% utilization of the available bus bandwidth just moving instructions around. Am I wrong in this? If anyone can provide me with information and/or analytic models with reasonable instruction mix assumptions, I would appreciate it. If the caches hold instructions as well as data, is there any way for the programmer to control the percentage of cache allocated for each? I would also appreciate any information on how Sequent makes use of the Intel code and data segment descriptors. Do they just create a single, huge segment for each? Do they share the same segment? Any information will be appreciated. Thanks, Tom Gerasch MITRE-Washington Software Engineering Center tomg@mitre.org -- Dr. Tom Gerasch, Lead Scientist DDN: tgerasch@mitre.org MITRE-Washington C3 Division tomg@mitre.org Software Engineering Center 7525 Colshire Drive (703) 883-7895