Path: utzoo!attcan!uunet!samsung!uakari.primate.wisc.edu!dali.cs.montana.edu!ogicse!intelhf!ichips!inews!iwarp.intel.com!csun!kithrup!sef From: sef@kithrup.COM (Sean Eric Fagan) Newsgroups: comp.arch Subject: Re: Register Count Message-ID: <1991Jan12.222106.20961@kithrup.COM> Date: 12 Jan 91 22:21:06 GMT References: <11566@pt.cs.cmu.edu> Organization: Kithrup Enterprises, Ltd. Lines: 20 In article <11566@pt.cs.cmu.edu> lindsay@gandalf.cs.cmu.edu (Donald Lindsay) writes: >In article > pcg@cs.aber.ac.uk (Piercarlo Grandi) writes: >>It is an old controversy, but let me repeat here: 90% of what passes for >>"optimizing" compilers are compilers that optimize for *space*, not >>time, ... Uhm... what makes you think they're so different? The MSC compiler optimizes for space, not execution time. However, the *86 architecture is such that, in most cases, optimizing for space also ends up with more efficient code. (In particular, CSE and other code removal techniques *do* result in faster code, as well as smaller.) On most RISC chips, the smallest code is quite often the fastest code. -- Sean Eric Fagan | "I made the universe, but please don't blame me for it; sef@kithrup.COM | I had a bellyache at the time." -----------------+ -- The Turtle (Stephen King, _It_) Any opinions expressed are my own, and generally unpopular with others.