Path: utzoo!attcan!uunet!fernwood!portal!cup.portal.com!mmm
From: mmm@cup.portal.com (Mark Robert Thorson)
Newsgroups: comp.arch
Subject: The Future of Buses (and Futurebus+)
Message-ID: <38005@cup.portal.com>
Date: 14 Jan 91 04:07:00 GMT
Organization: The Portal System (TM)
Lines: 18

In the earlier discussion of Futurebus+, the consensus seemed to be
that the model supported by Futurebus+ (i.e. processors and memory
connected by a bus or a network of buses and bus repeaters) is not
an interesting model because processors will be connected to
memory via proprietary on-board buses.  Standard buses will be
used for talking to high-bandwidth peripherals, and for these
purposes the features of Futurebus+ are overkill.

So what is the argument for Futurebus+?  Do its designers anticipate
future low silicon costs will make the cost of implementing
Futurebus+ an imperceptible drop in the bit bucket?  Or is there
some other technological development, such as multithreaded
operating systems, which will make the Futurebus+ model popular?

Will standard buses evolve toward simpler interfaces, more
appropriate for mass I/O?  Or will the CPU bus evolve into something
like (or exactly like) Futurebus+?  Or will standard buses get replaced
by something else, like dedicated buses?