Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!wuarchive!zaphod.mps.ohio-state.edu!think.com!snorkelwacker.mit.edu!shelby!neon!torrie
From: torrie@cs.stanford.edu (Evan Torrie)
Newsgroups: comp.arch
Subject: Re: On-Chip Cache Survey
Message-ID: <1991Feb8.020013.22133@Neon.Stanford.EDU>
Date: 8 Feb 91 02:00:13 GMT
References: <16444@sdcc6.ucsd.edu> <2369@inews.intel.com>
Sender: torrie@Neon.Stanford.EDU (Evan James Torrie)
Organization: Computer Science Department, Stanford University
Lines: 26

dlau@mipos2.intel.com (Dan Lau) writes:

>Off the top of my head, the following chips have on-chip cache (all
>on one single chip, as opposed to the Clipper, 88000 or RS6000, which
>have separate cache controller/memory chips which are used as a set):

>80486: 4K code, 4K data

>68040: 8K unified

  These should be reversed I believe...  
68040 4K code 4K data 
80486 8K unified

Also, be on the lookout for
MIPS R4000 8K data 8K code
Motorola 88110
TI Viking?

as examples of chips with on-chip cache.

-- 
------------------------------------------------------------------------------
Evan Torrie.  Stanford University, Class of 199?       torrie@cs.stanford.edu   
"If it weren't for your gumboots, where would you be?   You'd be in the
hospital, or in-firm-ary..."  F. Dagg