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From: mh2f+@andrew.cmu.edu (Mark Hahn)
Newsgroups: comp.arch
Subject: Re: R4000
Message-ID: <obgVpm200VpeQ4VmIa@andrew.cmu.edu>
Date: 8 Feb 91 03:39:30 GMT
References: <45448@mips.mips.COM> <1991Feb1.223326.18683@watdragon.waterloo.edu>,
	<45525@mips.mips.COM>
Organization: Carnegie Mellon, Pittsburgh, PA
Lines: 13
In-Reply-To: <45525@mips.mips.COM>

isn't MIPS's "superpiplining" just the common trick 
of sticking in a clock doubler?

would anyone care to comment on the argument
that "the amount of instruction-level parallelism 
that is available limits the benefit" of superscalar?
It seems like I saw simulation papers claiming
superscalar speedups of 2-3x.  besides, wouldn't
MIPS still have to resolve the same dependencies,
and thus be subject to the same limits?  
(assuming the r4000 isn't just a clock speedup.)

regards, mark