Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sun-barr!apple!apple.com!russell
From: russell@apple.com (Russell Williams)
Newsgroups: comp.arch
Subject: Re: Real Time/Cache
Message-ID: <12001@goofy.Apple.COM>
Date: 8 Feb 91 18:17:35 GMT
Sender: usenet@Apple.COM
Organization: Apple Computer
Lines: 11
References:<11190@pt.cs.cmu.edu> <90331.001007DXB132@psuvm.psu.edu> <11228@pt.cs.cmu.edu> <17999@cbmvax.commodore.com> <1991Jan28.174243.17814@src.honeywell.com> <2288@tuvie.UUCP> <1991Jan30.145327.4541@src.honeywell.com> <1991Jan31.005028.26850@fs7.ece.cmu.edu> <1991Feb3.174611.2998@fs7.ece.cmu.edu>

The Elxsi gamma CPU (running in the lab but never shipped before Elxsi 
U.S. quit R&D) implemented  cache partitioning  for real time support.  
Its 1 MB I and D caches could be independently partitioned up to 8 ways 
each.  The simple implementation (replacing a variable number of the high 
order address bits to the direct mapped cache) meant that partitions had 
to be power of two sizes, and that performance cost was negligable.   

A small piece of software handled partition allocation, sharing the 
largest unallocated partition among all the tasks that hadn't explicitly 
requested a partition.  Minor modifications were required to areas of the 
system software which handled cache flushing (e.g. for I/O).