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From: jab@duke.cs.duke.edu (John A. Board)
Newsgroups: comp.arch
Subject: Re: On-Chip Cache Survey
Summary: INMOS H1 programmable on-chip cache and/or user RAM
Message-ID: <666031773@umbriel.cs.duke.edu>
Date: 8 Feb 91 16:49:34 GMT
References: <16444@sdcc6.ucsd.edu>
Organization: Duke University Computer Science Dept.; Durham, N.C.
Lines: 20

In article <16444@sdcc6.ucsd.edu>, jlodman@beowulf.ucsd.edu (Michael Lodman) writes:
> ...
> I would appreciate people sending to me or posting lists of micros
> they know of with on-chip cache. User comments would be appreciated
> as well.
>
``Reliable rumor'' has it that the next generation Transputer (the H1,
due to be announced in April) has a 16 KByte unified cache that can also
be configured to act as on-chip (i.e. fast) user-addressable RAM.
I believe one can select the two 8K sections separately as Cache/RAM.
I'm not aware of any other chip that lets the user ``program'' the cache
in this manner, but then again I'm not omniscient....  Earlier Transputers
have had on-chip RAM only; no on-chip cache.  Perhaps someone from
SGS-Thomson/INMOS can comment further.

John Board                                   INET: jab@dukee.egr.duke.edu
Assistant Professor                            or  jab@duke.cs.duke.edu
Dept. Electrical Eng'g and Dept. Comp. Sci.  
Duke University                              FAX:   +1 (919) 684-4860
Durham NC USA                                VOICE: +1 (919) 660-5272