Path: utzoo!utgpu!news-server.csri.toronto.edu!bonnie.concordia.ca!thunder.mcrcim.mcgill.edu!snorkelwacker.mit.edu!mintaka!olivea!samsung!sdd.hp.com!hplabs!otter.hpl.hp.com!hpltoad!cdollin!kers From: kers@hplb.hpl.hp.com (Chris Dollin) Newsgroups: comp.arch Subject: Re: On-Chip Cache Survey Message-ID: Date: 8 Feb 91 14:14:28 GMT References: <16444@sdcc6.ucsd.edu> <2369@inews.intel.com> <1991Feb8.020013.22133@Neon.Stanford.EDU> Sender: news@hplb.hpl.hp.com (Usenet News Administrator) Organization: Hewlett-Packard Laboratories, Bristol, UK. Lines: 12 In-Reply-To: torrie@cs.stanford.edu's message of 8 Feb 91 02:00:13 GMT Nntp-Posting-Host: cdollin.hpl.hp.com The ARM3 (Acorn Risc Machine, version 3) has a 4Kb cache on-chip (instructions + data, I believe). Since the chip appears in machines with slow (ie, cheap) memory (no, I can't quote times), and clocks at around 30MHz, the cache is pretty much essential to get a performance improvement over the 8MHz ARM2. It certainly makes one hell of a difference on my A440. -- Regards, Kers. | "You're better off not dreaming of the things to come; Caravan: | Dreams are always ending far too soon."