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From: cet1@cl.cam.ac.uk (C.E. Thompson)
Newsgroups: comp.arch
Subject: Re: Vector processors, i860 (really: RS/6000)
Message-ID: <1991Feb5.150252.2094@cl.cam.ac.uk>
Date: 5 Feb 91 15:02:52 GMT
References: <1991Feb4.011858.12355@cs.uiuc.edu> <1991Feb4.023042.21714@cs.uiuc.edu> <1991Feb4.194521.8384@cs.uiuc.edu> <2896@charon.cwi.nl>
Reply-To: cet1@cl.cam.ac.uk (C.E. Thompson)
Organization: U of Cambridge Comp Lab, UK
Lines: 31

In article <2896@charon.cwi.nl> dik@cwi.nl (Dik T. Winter) writes:
>The RS6000 can issue three *different* kinds of instructions at the same time
>(where different is different from the different of the i860).
>--
and there have been similar postings in this thread. Misunderstandings tend
to arise here, because there are different constraints coming from different 
stages in the various pipelines:

1. The ICU can, on any one cycle, do all of:
   a. Execute a branch instruction
   b. Execute a condition register instruction
   c. Dispatch two other instructions to the FXU & FPU. These can be both
      fixed, both floating, or one of each.
2. The FXU can execute at most one fixed point instruction each cycle
   (and most such instructions do only take one cycle).
3. The FPU is bit more complicated because of the parallel load and 
   arithmetic pipelines, but sticking to arithmetic instructions, it can
   begin executing one new floating point operation each cycle. (They 
   usually have 2 or 3 cycle latency.) The operation can be a multiply-
   and-add, which you can count as two FLOPS if you want to.

To keep up a rate of two non-ICU-executed instructions per cycle therefore
requires equal numbers of fixed and floating-point instructions. However,
because both the FXU and FPU contain buffers of instructions issued by the
ICU and not yet executed, the instructions don't have to strictly alternate
in type, and it is not necessary for one of each type to be issued by the 
ICU on each cycle.

Chris Thompson
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