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From: kenton@abyss.zk3.dec.com (Jeff Kenton OSG/UEG)
Newsgroups: comp.arch
Subject: Re: Vector processors, i860
Message-ID: <539@decvax.decvax.dec.com.UUCP>
Date: 6 Feb 91 14:37:36 GMT
References: <798@nvuxl.UUCP> <1991Feb2.224442.12489@zoo.toronto.edu> <1991Feb4.011858.12355@cs.uiuc.edu> <1991Feb4.023042.21714@cs.uiuc.edu>
Sender: news@decvax.dec.com.UUCP
Reply-To: kenton@abyss.zk3.dec.com (Jeff Kenton OSG/UEG)
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In article <1991Feb4.023042.21714@cs.uiuc.edu>, gillies@cs.uiuc.edu (Don
Gillies) writes:
|> henry@zoo.toronto.edu (Henry Spencer) writes:
|> 
|> From a naive standpoint, isn't an i860 functionally similar to an IBM
|> 6000 cpu?
|> 
|> Does IBM know something about processor scheduling and compiler
|> writing that the rest of the world doesn't?  If compiler writers go
|> "up the wall" trying to generate i860 code, perhaps it's because they
|> are ignorant of, or unwilling to develop, effective scheduling
|> techniques.
|> 

The i860 has the ability to execute up to 3 instructions at a time, giving
a theoretical possibility of 120 mips at 40MHz.  Unfortunately, you can
only do this with specific combinations of instructions (and by changing modes
and incurring a startup penalty).

For normal programming (even in assembler) this parallelism is rarely
available,
and finding it with a compiler is difficult.  Generally, the i860 performs like
a normal processor -- its mips rating is its clock speed minus some percentage
for pipeline stalls and memory delays.

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==	jeff kenton		Consulting at kenton@decvax.dec.com        ==
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