Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!elroy.jpl.nasa.gov!lll-winken!ames!uhccux!munnari.oz.au!metro!cluster!mrj
From: mrj@cluster.cs.su.oz.au (Mark James)
Newsgroups: comp.arch
Subject: A Fast Memory Architecture
Keywords: DRAM
Message-ID: <2012@cluster.cs.su.oz.au>
Date: 9 Feb 91 03:53:36 GMT
Organization: Dept. of Comp. Science, Uni of Sydney, Australia
Lines: 19

Memory reference profiles for most applications show a moderately
sized set of very active clumps with little access elsewhere.
One possible DRAM configuration to match this would be to use
page mode DRAMS and spreading adjacent pages systematically
or randomly across the different chips.  Each chip has a
different currently active page allowing quick access to almost
as many pages as there are chips - assuming you have randomised
the pages across the chips properly.  All you would need to
implement this would be a more complex, MMU like, DRAM controller.

Motorola's DSP96002 uses a separate active page for each of its
three memory spaces, but does anyone know of any implementations
going the whole hog?

I think I read that someone has patented this configuration with
the addition of even quicker access to one location per chip through
chip enable.

Mark