Path: utzoo!utgpu!news-server.csri.toronto.edu!bonnie.concordia.ca!nstn.ns.ca!news.cs.indiana.edu!noose.ecn.purdue.edu!samsung!uunet!mcsun!cernvax!chx400!chx400!bernina!neptune!inf.ethz.ch!brandis From: brandis@inf.ethz.ch (Marc Brandis) Newsgroups: comp.arch Subject: Re: Vector processors, i860 Message-ID: <24063@neptune.inf.ethz.ch> Date: 6 Feb 91 07:50:08 GMT References: <798@nvuxl.UUCP> <1991Feb2.224442.12489@zoo.toronto.edu> <1991Feb4.011858.12355@cs.uiuc.edu> <1991Feb4.023042.21714@cs.uiuc.edu> <1991Feb4.194521.8384@cs.uiuc.edu> Sender: news@neptune.inf.ethz.ch Reply-To: brandis@inf.ethz.ch (Marc Brandis) Organization: Departement Informatik, ETH, Zurich Lines: 31 In article <1991Feb4.194521.8384@cs.uiuc.edu> gillies@cs.uiuc.edu (Don Gillies) writes: > >Someone has informed me that the i860 can only issue three *different* >kinds of instructions at the same time (i.e. Integer, FPU, branch), >while the IBM 6000 can issue three instructions of the *same* kind at >the same time (i.e. FPU, FPU, FPU). > You were misinformed about both the i860 and the IBM S/6000. The i860 can only issue two instructions at once, where one has to be an integer instruction (branch counts as integer instruction) and one has to be a floating point instruction. Moreover, you have to statically schedule these instructions. That is, you enter a special mode (so-called dual instruction mode), in which the i860 reads two instructions every cycle and issues the first one to the integer unit and the second to the floating point unit. However, the floating-point instruction can be a multiply-and-add instruction, so that you can say that three operations may be issued at once in this mode. The IBM S/6000, on the other hand, can issue four instructions at once, but all have to be of a different kind: one integer, one fp, one branch and one condition-code operation. The fp instruction can be multiply-and-add, so you get a maximum of 5 operations per cycle (but this is an instruction mix that you will never find). The S/6000 is dynamically scheduled. That is, the programmer implements just a sequential stream of instructions, the hardware determines what can be issued in parallel. Marc-Michael Brandis Computer Systems Laboratory, ETH-Zentrum (Swiss Federal Institute of Technology) CH-8092 Zurich, Switzerland email: brandis@inf.ethz.ch