Newsgroups: comp.arch
Path: utzoo!henry
From: henry@zoo.toronto.edu (Henry Spencer)
Subject: Re: A Fast Memory Architecture
Message-ID: <1991Feb10.013525.1317@zoo.toronto.edu>
Organization: U of Toronto Zoology
References: <2012@cluster.cs.su.oz.au>
Date: Sun, 10 Feb 1991 01:35:25 GMT

In article <2012@cluster.cs.su.oz.au> mrj@cluster.cs.su.oz.au (Mark James) writes:
>Memory reference profiles for most applications show a moderately
>sized set of very active clumps with little access elsewhere.
>One possible DRAM configuration to match this would be to use
>page mode DRAMS and spreading adjacent pages systematically
>or randomly across the different chips.  Each chip has a
>different currently active page ...

A major problem with this is that DRAMs typically are only one bit wide.
So the minimum unit of memory is a 32-chip bank, not a single chip.
You can buy wider DRAMs, but in general they need extra pins, and this
means a bigger package that eats more board space; there is *very* strong
economic and practical pressure toward 1-bit-wide DRAMs, and this will
continue as long as a substantial number of DRAMs are needed to meet
a system's memory requirements.  (Of late, the software people's memory
needs have shown a regrettable ability to match or exceed the growth in
chip capacity.)
-- 
"Maybe we should tell the truth?"      | Henry Spencer at U of Toronto Zoology
"Surely we aren't that desperate yet." |  henry@zoo.toronto.edu   utzoo!henry