Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!usc!zaphod.mps.ohio-state.edu!pacific.mps.ohio-state.edu!linac!att!pacbell.com!ucsd!sdcc6!beowulf!jlodman From: jlodman@beowulf.ucsd.edu (Michael Lodman) Newsgroups: comp.arch Subject: Re: On-Chip Cache Survey Message-ID: <16513@sdcc6.ucsd.edu> Date: 9 Feb 91 23:08:01 GMT References: <16444@sdcc6.ucsd.edu> <2369@inews.intel.com> <1991Feb8.020013.22133@Neon.Stanford.EDU> Sender: news@sdcc6.ucsd.edu Organization: CSE Department, UC San Diego Lines: 15 Nntp-Posting-Host: beowulf.ucsd.edu In article <1991Feb8.020013.22133@Neon.Stanford.EDU> torrie@cs.stanford.edu (Evan Torrie) writes: >Motorola 88110 > >as examples of chips with on-chip cache. Is Motorola planning on adding a cache on-chip to the 88100? Last time I checked the cache was contained in the 88200 CMMU. Thanks to all who have replied so far. I've been out of the CPU business for a while, and plain forgot about the small 68020 cache. -- Michael Lodman Department of Computer Science Engineering University of California, San Diego jlodman@cs.ucsd.edu (619) 672-1673