Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sun-barr!apple!amdcad!mozart.amd.com!electron!scott
From: scott@electron.amd.com (Scott McMahon)
Newsgroups: comp.arch
Subject: Re: On-Chip Cache Survey
Summary: 29K BTC
Message-ID: <1991Feb10.023006.13121@mozart.amd.com>
Date: 10 Feb 91 02:30:06 GMT
References: <16444@sdcc6.ucsd.edu>
Sender: scott@amd.com
Followup-To: comp.arch
Organization: Advanced Micro Devices, Austin, TX
Lines: 13

In article <16444@sdcc6.ucsd.edu> jlodman@beowulf.ucsd.edu (Michael Lodman) writes:
| I would appreciate people sending to me or posting lists of micros
| they know of with on-chip cache. User comments would be appreciated
| as well.

The Am29000 has a 512 byte Branch Target Cache (yes, an instruction
cache variant). The Am29050 has a 1 kbyte dual mode BTC (programmable
number of sets vs block size tradeoff).

-Scott
--
Scott McMahon - 29k Advanced Processor Development - Advanced Micro Devices
scott@amd.com                                        (800) 531-5202 x54985