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From: agn@unh.cs.cmu.edu (Andreas Nowatzyk)
Newsgroups: comp.arch
Subject: Re: A Fast Memory Architecture
Message-ID: <11878@pt.cs.cmu.edu>
Date: 10 Feb 91 22:32:37 GMT
References: <2012@cluster.cs.su.oz.au> <1991Feb10.013525.1317@zoo.toronto.edu>
Organization: Carnegie-Mellon University, CS/RI
Lines: 37

>> mrj@cluster.cs.su.oz.au (Mark James) writes:
>> ... proposal to use page-mode (or static column) mode access to speed up
>> DRAM systems in the presence of access locality. [something like the
>> memory system of the old Sun 4/110]

> henry@zoo.toronto.edu (Henry Spencer) replies:
> ... claims major problem due *very* strong economic incentive for *1 DRAMs

Historically there was a strong motivation for by 1 DRAMs, but things have
changed considerably. First, packaging technology has advanced: with TSOP
packaging, the 2 extra pins for a *4 organization do not increase package
size and are virtually free. In fact, even with the current SOJ packages,
there are several unused pin places near the center. Basically, the die size
of the DRAM chip dictates package size, not pin-count (for DRAMs > 1 Mbit).

Second, by 1 organizations become too cumbersome: consider a 64bit SIMM
with 16 Mbit chips: "Sorry, but 128 Mbytes IS our smallest SIMM" :-)

Third, by 1 organizations waste a lot of memory bandwidth. Internally, large
DRAMs are composed of many independent arrays, but only 1 bit of one array
is accessed per cycle.

Consequently, there are plenty by 4, by 8 and by 16 (!) DRAM devices in the
pipe, with very little difference in device cost and no difference in package
size.

The clever use of page mode and/or static column mode seems to be subject of
another Hyatt patent.

There are numerous other proposals to improve the DRAM bandwidth. For
example the integration of a fast SRAM into a DRAM with the ability to copy
large blocks of memory between the SRAM and the DRAM in one cycle.

Other ongoing efforts try to replace the normal TTL interface of DRAMs with
extremely fast signalling schemes to increase the bandwidth between the data
stored in the sense-amplified columns of the DRAM and the outside world.
Again, most of these schemes use 4 or 8 bit interfaces.