Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!isis!jwoehr
From: jwoehr@isis.cs.du.edu (Jack J. Woehr)
Newsgroups: comp.lang.forth
Subject: Re: TOS in a CPU register
Summary: Depends on chip
Keywords: chip,architecture,cache,stack,next
Message-ID: <1991Feb9.032229.2276@isis.cs.du.edu>
Date: 9 Feb 91 03:22:29 GMT
References: <1134@pcsbst.pcs.com>
Reply-To: jwoehr@isis.UUCP (Jack J. Woehr)
Organization: Math/CS, University of Denver
Lines: 61

In article <1134@pcsbst.pcs.com> hgw@rht32.pcs.com (h.-g. willers) writes:
>Can anyone in the Forth-Comunity domment on the following issue:
>
>Given an indirect threaded FORTH for a RISC-procesor (R3000 or i860).
>What is the best implementation (concerning speed) for Top-of-Stack,
>i.e.
>	TOS not in a CPU register
>	TOS in     a CPU register
>	TOS and NOS in a CPU register
>	TOS and NOS and NOS+1 ....

	Depends on the chip architecture. On the FRISC-32 (marketed
commercially by Silicon Composers as the SC32), the top four stack
items are registers, so la-dee-dah! It's all in the silicon.

	On the other hand, TOS in a register is about all that most
conventional small CISC chips will manage efficiently. I cache TOS
in Vesta's Forth-83i96 for the SBC196 (Intel 80196-based single board).
In that case, NOS in a register, even though the 80196 has PLENTY regs,
would be an license to thrash.

	The advantage on the SBC196 is that address modes work on the
80C196 typically dictate that one operand be register direct mode and the
other be any of the oblique modes ... so were TOS *not* cached, "+" would
be:

	POP R0
	ADD R0,[SP]
	ST  R0,[SP]
	RETURN

	whereas cached it's

	ADD TOS,[SP]+
	RETURN

	for over a 50 % advantage in this particular case.

	You end up giving some of the speed back since every time you
push a literal (or whatever) to the stack it's two operations

	PUSH TOS
	LD   TOS,#FOOBAR

	but my guesstimate is that in Vesta Forth-83i96 we are saving over
ten percent execution overhead by cacheing TOS.

	I say "guesstimate" since the advantage was so obvious prima
facia that we never coded the system any other way.

	Your question is intriguing ... I have the i860 manuals on my shelf
but have never played with this 64-bit graphics engine ... what's up
your sleeve? Would love to see your work after you get she up and running!

	Keep us all posted, and let us know what you conclude after you
have counted all the cycles like good engineers :-)
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