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From: koopman@a.gp.cs.cmu.edu (Philip Koopman)
Newsgroups: comp.lang.forth
Subject: Re: TOS in a CPU register
Summary: TOS is faster, NOS is slower
Keywords: chip,architecture,cache,stack,next
Message-ID: <11863@pt.cs.cmu.edu>
Date: 9 Feb 91 15:32:09 GMT
References: <1134@pcsbst.pcs.com> <1991Feb9.032229.2276@isis.cs.du.edu>
Organization: Carnegie-Mellon University, CS/RI
Lines: 23

*** This is posted as a favor to Igor Agamirzian ***

Organization: Leningrad Institute for Informatics AS USSR
From: Igor Agamirzian <igor@iias.spb.su>

We have and experience with different implementation of the top of the stack in
the AstroFORTH system for the IBM PC. In the standard system we use a hardware
stack of i8086/i80286 without top on the register. Using the target compiler of
the AstroFORTH, we implemented two different types of stack top: with TOS on a
register and with TOS and NOS on the registers, and checked the speed on the
standard banchmark tests (BYTE, 1984, v.9, No 12 and FORTH Dimensions III/1).
Our result was: taking standard implementation for 100% of execution speed, we
got 108% with the one register implementation, and 95% with two registers. I
think, that the result shows, that handling of two register top takes more time,
than the economy on readiness of the arguments for binary operations gives. Of
course, theese results may differ on different types of processors, though in
any case there must be a threshold of effectiveness for the number of registers
for the top of the stack representation.
-- 
-- Igor Agamirzian

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