Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!usc!zaphod.mps.ohio-state.edu!pacific.mps.ohio-state.edu!linac!att!ucbvax!MITCH.ENG.SUN.COM!wmb
From: wmb@MITCH.ENG.SUN.COM (Mitch Bradley)
Newsgroups: comp.lang.forth
Subject: TOS in a register
Message-ID: <9102100539.AA07898@ucbvax.Berkeley.EDU>
Date: 9 Feb 91 07:43:29 GMT
Sender: usenet@ucbvax.BERKELEY.EDU
Reply-To: Mitch Bradley <wmb%MITCH.ENG.SUN.COM@SCFVM.GSFC.NASA.GOV>
Organization: The Internet
Lines: 16

> Given an indirect threaded FORTH for a RISC-procesor (R3000 or i860).
> What is the best implementation (concerning speed) for Top-of-Stack,

My experience agrees with Phil Koopman's.  In both my C Forth 83 and
Sun Forth-SPARC implementations, TOS in a register was worth about 10%,
and using more than one stack cache register was more trouble than I
was willing to undertake.

In the Sun Forth-SPARC case, if I had it to do over again, I would not
have put the top of the stack in a register.  In my judgement, the 10%
speed advantage was not worth the trouble of explaining to users how to
manage the TOS register inside CODE words.

Speed isn't everything.

Mitch Bradley, wmb@Eng.Sun.COM