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From: smith1@uicbert.eecs.uic.edu (Ross Smith)
Newsgroups: comp.lsi
Subject: vhdl puzzle
Summary: simulation of F <= D + E; does not work
Keywords: vhdl
Message-ID: <1991Feb6.155659.23123@uicbert.eecs.uic.edu>
Date: 6 Feb 91 15:56:59 GMT
Distribution: comp
Organization: University of Illinois at Chicago
Lines: 15

Given the following architecture body.
D and E are converted to correct values, but F gives a 0.
Any ideas why this doesn't work (especially since it works elsewhere)?

architecure adder of adder is
 signal d,e,f : integer;
 begin
  process (add_enable, add_in1, add_in2)
    if (add_enable, = '1') then
      d <= bin_int2(add_in1); -- convert 32-bit bit array to integer 
      e <= bin_int3(add_in2); -- convert 40-bit bit array to integer 
      f <= (d + e); -- add the integers together
    end if;
  end process;
end adder;