Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!usc!sdd.hp.com!think.com!mintaka!bloom-beacon!dont-send-mail-to-path-lines From: aboulham@iro.umontreal.ca Newsgroups: comp.lsi Subject: Re: vhdl puzzle Message-ID: Date: 6 Feb 91 16:58:05 GMT Sender: daemon@athena.mit.edu (Mr Background) Organization: The Internet Lines: 29 ------- > Given the following architecture body. > D and E are converted to correct values, but F gives a 0. > Any ideas why this doesn't work (especially since it works elsewhere)? > architecure adder of adder is > signal d,e,f : integer; > begin > process (add_enable, add_in1, add_in2) > if (add_enable, = '1') then > d <= bin_int2(add_in1); -- convert 32-bit bit array to integer > e <= bin_int3(add_in2); -- convert 40-bit bit array to integer > f <= (d + e); -- add the integers together > end if; > end process; > end adder; ---------- The problem here, is that f takes the present values of d and e (which are either 0 or the left value of the integer type). The updated values of d and e will be present on the next delta cycle. One possibility is to add d and e to the sensititvity list of the process. You will get the correct value on f some delta cycles later. -------