Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sun-barr!apple!altos!altos86!rcollins
From: rcollins@altos86.Altos.COM (Robert Collins)
Newsgroups: comp.sys.ibm.pc.hardware
Subject: Re: Why I lower my CPU speed to 17.5MHz
Message-ID: <4710@altos86.Altos.COM>
Date: 7 Feb 91 21:02:05 GMT
References: <5540@bwdls58.UUCP> <1991Feb6.055458.7488@d.cs.okstate.edu>
Reply-To: rcollins@altos86.UUCP (Robert Collins)
Organization: Altos Computer Systems, San Jose, CA
Lines: 47

In article <1991Feb6.055458.7488@d.cs.okstate.edu> ong@d.cs.okstate.edu (ONG ENG TENG) writes:
>From article <5540@bwdls58.UUCP>, by mlord@bwdls58.bnr.ca (Mark Lord):
>> 
>> When one speeds up the CPU by changing the crystal, as ONG has done, 
>> the expansion bus will also be run faster in most cases.  Since it is
>> run at 1/2 CPU speed, this means 10Mhz instead of the standard 8Mhz.
>
>Well, you might be right, but there is a good (and obvious) reason 
>to contradict.  Since my motherboard allows me to switch down 
>to 8MHz operation regardless of the "main" oscillators I have 
>(32MHz, 35MHz, or 40MHz for 16MHz, 17.5MHz, or 20MHz operations).  
>It would be more reasonable for them to use the 8MHz crystal for 
>i/o bus clock instead.  Remember, I "change" oscillator by putting one
>in the optional slot, the original 32MHz (for 16MHz operation) oscillator
>remains on the motherboard (it is soldered in).
>

Didn't anybody read my posting on this subject?  I've seen ONG quote many
people in his subsequent postings, but he missed mine!  Who cares?  How
many of you have ported a BIOS over to the NEAT or LEAP chipset (ONG has
the NEAT chipset)?  How many of you have read the NEAT spec?  The one thing
lacking in this whole conversation is a discussion of the hardware design
of the motherboard.

The NEAT and LEAP chipsets have the ability to run the BUS CLOCK (BCLK)
synchronously or asynchronously to the CPU CLOCK.  If it is run in async
mode, then you better guarantee that your hardware was design with a
crystal dedicated to running the peripheral BUS.  If the hardware wasn't
designed to run the bus asyncronously, then BCLK is a function of CLK.
CLK / 2, CLK / 3, CLK / 4, CLK / 6 are some, but probably not all the
divisors that can drive BCLK.  If ONG's computer was designed to 
drive the bus syncronously, then increasing CLK will increase BCLK, and
as many of you have mentioned, is probably the cause of the HD failure.
However, regardless of a secondary crystal socket, and maybe a jumper
to enable the socket, this does not imply, nor guarantee that BCLK can
run asyncronously.  The BIOS must program NEAT for ASYNC mode for it
to work, AND there must be a secondary crystal specifically for this
purpose.

So, now let's discuss the hardware...ONG?  How was it designed?


-- 
"Worship the Lord your God, and serve him only."  Mat. 4:10
Robert Collins                 UUCP:  ...!sun!altos86!rcollins
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