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From: ong@d.cs.okstate.edu (ONG ENG TENG)
Newsgroups: comp.sys.ibm.pc.hardware
Subject: Re: Why I lower my CPU speed to 17.5MHz
Message-ID: <1991Feb8.172115.12079@d.cs.okstate.edu>
Date: 8 Feb 91 17:21:15 GMT
References: <4710@altos86.Altos.COM>
Organization: Oklahoma State University
Lines: 34

From article <4710@altos86.Altos.COM>, by rcollins@altos86.Altos.COM (Robert Collins):
> Didn't anybody read my posting on this subject?  I've seen ONG quote many
> people in his subsequent postings, but he missed mine!  Who cares?  How
> many of you have ported a BIOS over to the NEAT or LEAP chipset (ONG has
> the NEAT chipset)?  How many of you have read the NEAT spec?  The one thing
> lacking in this whole conversation is a discussion of the hardware design
> of the motherboard.
> 
> The NEAT and LEAP chipsets have the ability to run the BUS CLOCK (BCLK)
> synchronously or asynchronously to the CPU CLOCK.  If it is run in async
> mode, then you better guarantee that your hardware was design with a
> crystal dedicated to running the peripheral BUS.  If the hardware wasn't
> designed to run the bus asyncronously, then BCLK is a function of CLK.
> CLK / 2, CLK / 3, CLK / 4, CLK / 6 are some, but probably not all the
> divisors that can drive BCLK.  If ONG's computer was designed to 
> drive the bus syncronously, then increasing CLK will increase BCLK, and
> as many of you have mentioned, is probably the cause of the HD failure.
> However, regardless of a secondary crystal socket, and maybe a jumper
> to enable the socket, this does not imply, nor guarantee that BCLK can
> run asyncronously.  The BIOS must program NEAT for ASYNC mode for it
> to work, AND there must be a secondary crystal specifically for this
> purpose.
> 
> So, now let's discuss the hardware...ONG?  How was it designed?

Woo... touchy, touchy.  I probably missed your post since our machine 
goes down twice a week, and I sometimes find followups that 
has no original post. 

My CPU is running on CLK/2, while the bus is running on ATBUS.  I believe
they are asyncronous.  I think the CLK is the main crystal at 32MHz and
35MHz after I changed the position of the shorting block on the MB.  I
looked around but could not find the spec for ATBUS.  Does anyone have
any idea?