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From: kenton@abyss.zk3.dec.com (Jeff Kenton OSG/UEG)
Newsgroups: comp.sys.mips
Subject: Load Delays -- a question
Message-ID: <540@decvax.decvax.dec.com.UUCP>
Date: 6 Feb 91 14:47:09 GMT
Sender: news@decvax.dec.com.UUCP
Reply-To: kenton@abyss.zk3.dec.com (Jeff Kenton OSG/UEG)
Lines: 21


A question regarding delays when loading words from memory:

	instruction 0:	lw	t0,foo
	instruction 1:
	instruction 2:
	instruction 3:

When is the data available in t0? If the data word "foo" is in the cache, it
is available by instruction 2.  If it is not cached and you have to go to
memory do you have to wait longer? If you have to wait for memory does the
processor stall? Always? Or only if you try to use the results of the "lw"
in t0?

Thanks for any help.


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==	jeff kenton		Consulting at kenton@decvax.dec.com        ==
==	(617) 894-4508			(603) 881-0011			   ==
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