Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sdd.hp.com!zaphod.mps.ohio-state.edu!mips!winchester!mash From: mash@mips.COM (John Mashey) Newsgroups: comp.sys.mips Subject: Re: What are the new features in MIPS-II instruction set? Message-ID: <45673@mips.mips.COM> Date: 7 Feb 91 19:54:14 GMT References: Sender: news@mips.COM Reply-To: mash@mips.COM (John Mashey) Organization: MIPS Computer Systems, Inc. Lines: 32 In article qzhe1@cs.aukuni.ac.nz (Qun Zheng ) writes: >MIPS-II does not use delayed-load. Why? > >Most MIPS instructions are RRR/RRI type. So how is MEM stage justified? I know >the address calculation is done in EX stage. But this calculation can be done >is one instruction and then use another instruction to do indirect access. So >EX stage uses ALU for ALU operations and accesses memory for load/store. Note >that RISC never encourage people to program in assembly level, so not much in- >convenience here. Maybe because lots of load/stores used in programs? > >It does not have to any performence gain by changing the pipeline. But there >must be some important factors in the design. Mind you informative/intelligent >netters give me some insight. I think what you're proposing is akin to the AMD 29K, where the loads and stores cannot have offsets, i.e. 0(RX) is only addressing mechanism, i.e. instead of: lw r2, 10(r3) you do something like add r4,r3,10 lw r2, 0 (r4) and the reason you don't do it is that loads and stores are usually 30% of a program, and if you do the cycle count analysis, it's better to include the offset calculation inside the instruction, rather than use 2 instructions much of the time. I'd guess that you need to do 2 instructions at least 70% of the time, or more. -- -john mashey DISCLAIMER: UUCP: mash@mips.com OR {ames,decwrl,prls,pyramid}!mips!mash DDD: 408-524-7015, 524-8253 or (main number) 408-720-1700 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086