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From: mash@mips.COM (John Mashey)
Newsgroups: comp.sys.mips
Subject: Re: Load Delays -- a question
Message-ID: <45672@mips.mips.COM>
Date: 7 Feb 91 19:40:36 GMT
References: <540@decvax.decvax.dec.com.UUCP>
Sender: news@mips.COM
Reply-To: mash@mips.COM (John Mashey)
Organization: MIPS Computer Systems, Inc.
Lines: 27

In article <540@decvax.decvax.dec.com.UUCP> kenton@abyss.zk3.dec.com (Jeff Kenton OSG/UEG) writes:

>A question regarding delays when loading words from memory:
>
>	instruction 0:	lw	t0,foo
>	instruction 1:
>	instruction 2:
>	instruction 3:
>
>When is the data available in t0? If the data word "foo" is in the cache, it
>is available by instruction 2.  If it is not cached and you have to go to
>memory do you have to wait longer? If you have to wait for memory does the
>processor stall? Always? Or only if you try to use the results of the "lw"
>in t0?

foo becomes available in instruction 2.
if it is a cache miss, the main pipeline stalls, does the refill, and
continues, regardless of how far off the usage of foo might occur.
Do NOT, repeat do NOT ever assume that in instruction 1, that the
data in t0 is that previous to instruction 0.  this is "undefined",
on purpose, because, for example, MIPS-II processors include the interlock,
so that instruction 1, if it uses t0, will stall.  (i.e., R6000/R4000).
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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