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From: jfc@athena.mit.edu (John F Carr)
Newsgroups: comp.sys.mips
Subject: Re: Load Delays -- a question
Message-ID: <1991Feb9.221451.22230@athena.mit.edu>
Date: 9 Feb 91 22:14:51 GMT
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Why did the original design not have the load interlock, and why does the
processor stall on a cache miss?  Do MIPS-2 processors act the same way on a
cache miss?  Making the load delay optional increases code density and makes
the compiler's job easier.

--
    John Carr (jfc@athena.mit.edu)