Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!mips!hal!mark
From: mark@mips.COM (Mark G. Johnson)
Newsgroups: comp.sys.mips
Subject: Re: Load Delays -- a question
Message-ID: <45753@mips.mips.COM>
Date: 10 Feb 91 16:10:09 GMT
Sender: news@mips.COM
Lines: 10

In article <1991Feb9.221451.22230@athena.mit.edu> jfc@athena.mit.edu (John F Carr) writes:
   >
   >Why did the original design not have the load interlock, and why
   >does the processor stall on a cache miss?
   >

Unfortunately this sounds very much like a classroom assignment.
Usually "the net" lets such questions go unanswered, lest the
poster be robbed of the opportunity of figuring out the answer
for her/himself.