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From: jfc@athena.mit.edu (John F Carr)
Newsgroups: comp.sys.mips
Subject: Re: Load Delays -- a question
Message-ID: <1991Feb11.043136.14845@athena.mit.edu>
Date: 11 Feb 91 04:31:36 GMT
References: <45672@mips.mips.COM> <1991Feb9.221451.22230@athena.mit.edu> <45762@mips.mips.COM>
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Organization: Massachusetts Institute of Technology
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In article <45762@mips.mips.COM> cprice@mips.COM (Charlie Price) writes:

>> and why does the
>>processor stall on a cache miss?  Do MIPS-2 processors act the same way on a
>>cache miss?

>What else is there to do?

>The only way not to stall when the instruction or data that you 
>want isn't available is if you are prepared to forge ahead and 
>try to execute instructions out of order.

I meant cache miss for data, not instruction fetch.  If the data being
loaded is not in cache, it should be possible to continue anyway with
unrelated instructions.  This does require parts of the processor to stall
when the data is needed if the load takes longer than expected, but the
newer MIPS processors do this anyway.  With such a design, the assembler
would put as many unrelated instructions as possible after a load.

I brought this up because I do much of my programming on an IBM RT, which
allows 2 outstanding load operations which normally need 5 cycles to
complete.  If you are accessing slower memory (such as an I/O device), data
takes longer to become available but the processor doesn't stop unless it
needs to.  I was surpised that a newer architecture with a faster clock rate
had a simpler way of handling load delay.

Over the next few months I will be running some simulations on a MIPS-based
workstation.  I expect the data size will need to be larger than the cache
size, so I will be getting a lot of cache misses.  The decision to have the
processor wait until data is in cache makes the change when a program
exceeds cache size larger than it would otherwise be.  I've never designed a
microprocessor nor have I ever taken any courses on this subject, but it
seems to me that stalling on loads only when the data is needed would have
been a better choice.  no-ops could be eliminated, performance could be
increased for some programs, and it would not have been necessary to change
the instruction set later when the load delay time changed.

--
    John Carr (jfc@athena.mit.edu)