Path: utzoo!censor!comspec!humvax!becker!ncrcan!attcan!uunet!cs.utexas.edu!wuarchive!udel!princeton!njin!paul.rutgers.edu!chain From: chain@paul.rutgers.edu (Chain Lee) Newsgroups: alt.sources Subject: X11R4 patch for SCO XENIX (part07) Message-ID: Date: 7 Jan 91 02:26:20 GMT Organization: Rutgers Univ., New Brunswick, N.J. Lines: 1142 *** X11R4.ORIG/mit/server/ddx/xenix/trident/vgaHWCntl.c Sun Jan 6 01:04:01 1991 --- X11R4/mit/server/ddx/xenix/trident/vgaHWCntl.c Wed Nov 14 22:03:52 1990 *************** *** 0 **** --- 1,529 ---- + /* + * Copyright IBM Corporation 1987,1988,1989 + * + * All Rights Reserved + * + * Permission to use, copy, modify, and distribute this software and its + * documentation for any purpose and without fee is hereby granted, + * provided that the above copyright notice appear in all copies and that + * both that copyright notice and this permission notice appear in + * supporting documentation, and that the name of IBM not be + * used in advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * + * IBM DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING + * ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL + * IBM BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR + * ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, + * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, + * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + * + */ + + #define PCIO + #ifndef i386 + #define i386 + #endif + + extern unsigned char inb(); + extern void outb(); + extern void outw(); + + #include "vgaVideo.h" + #include "vgaReg.h" + #include "vgaSave.h" + + + /* + * HARDWARE REGISTER USAGE : + ******* EVERYTHING + */ + + void + save_vga_state( VS ) + register struct vga_video_hardware_state *VS ; + { + register IO_Address Target_Reg ; /* if mono == 0x3B0, if color == 3D0 */ + register IO_Address Base_Reg ; /* if mono == 0x3B0, if color == 3D0 */ + + /* Read General Registers */ + VS->Feature_Control = inb( 0x3CA ) ; + VS->Video_Enable = inb( 0x3C3 ) ; + Base_Reg = ( ( VS->Misc_Output_Reg = inb( 0x3CC ) ) & 1 ) ? 0x3D0 : 0x3B0 ; + VS->Input_Status_0 = inb( 0x3C2 ) ; + /* Initialize Flip-Flop */ + VS->Input_Status_1 = inb( Base_Reg + 0xA ) ; + + /* Save Attribute Registers 03C0 & 03C1 */ + /* + INTS_OFF() ; + */ + VS->Attr_Addr_Reg = inb( 0x3C0 ) ; /* Save Existing Index First */ + /* Target_Reg Used As Scrap */ + for ( Target_Reg = 0 ; Target_Reg <= 0xF ; Target_Reg++ ) { + outb( 0x3C0, (unsigned char) Target_Reg ) ; + /* Read It, Save It, Then Write It Back */ + outb( 0x3c0, ( VS->Palette[Target_Reg] = inb( 0x3C1 ) ) ) ; + } + outb( 0x3c0, 0x30 ) ; + outb( 0x3c0, ( VS->Attr_Mode = inb( 0x3C1 ) ) ) ; + outb( 0x3c0, 0x31 ) ; + outb( 0x3c0, ( VS->Overscan_Color = inb( 0x3C1 ) ) ) ; + outb( 0x3c0, 0x32 ) ; + outb( 0x3c0, ( VS->Color_Plane_En = inb( 0x3C1 ) ) ) ; + outb( 0x3c0, 0x33 ) ; + outb( 0x3c0, ( VS->Horiz_PEL_Pan = inb( 0x3C1 ) ) ) ; + outb( 0x3c0, 0x34 ) ; + outb( 0x3c0, ( VS->Color_Select = inb( 0x3C1 ) ) ) ; /* Attr_Addr_Reg == 14 */ + /* Re-Enable Video Access To The Color Palette */ + /* + INTS_ON() ; + */ + + /* Save Crt Controller Registers 03?4 & 03?5 */ + VS->Index_Reg = inb( Target_Reg = ( Base_Reg += 0x4 ) ) ; + outb( Base_Reg, 0x00 ) ; + VS->Horiz_Total = inb( ++Target_Reg ) ; + outb( Base_Reg, 0x01 ) ; + VS->Horiz_End = inb( Target_Reg ) ; + outb( Base_Reg, 0x02 ) ; + VS->H_Blank_Start = inb( Target_Reg ) ; + outb( Base_Reg, 0x03 ) ; + VS->H_Blank_End = inb( Target_Reg ) ; + outb( Base_Reg, 0x04 ) ; + VS->H_Retrace_Start = inb( Target_Reg ) ; + outb( Base_Reg, 0x05 ) ; + VS->H_Retrace_End = inb( Target_Reg ) ; + outb( Base_Reg, 0x06 ) ; + VS->Vert_Total = inb( Target_Reg ) ; + outb( Base_Reg, 0x07 ) ; + VS->Overflow = inb( Target_Reg ) ; + outb( Base_Reg, 0x08 ) ; + VS->Preset_Row_Scan = inb( Target_Reg ) ; + outb( Base_Reg, 0x09 ) ; + VS->Max_Scan_Line = inb( Target_Reg ) ; + outb( Base_Reg, 0x0A ) ; + VS->Cursor_Start = inb( Target_Reg ) ; + outb( Base_Reg, 0x0B ) ; + VS->Cursor_End = inb( Target_Reg ) ; + outb( Base_Reg, 0x0C ) ; + VS->Start_Addr_Hi = inb( Target_Reg ) ; + outb( Base_Reg, 0x0D ) ; + VS->Start_Addr_Lo = inb( Target_Reg ) ; + outb( Base_Reg, 0x0E ) ; + VS->Cursor_Loc_Hi = inb( Target_Reg ) ; + outb( Base_Reg, 0x0F ) ; + VS->Cursor_Loc_Lo = inb( Target_Reg ) ; + outb( Base_Reg, 0x10 ) ; + VS->V_Retrace_Start = inb( Target_Reg ) ; + outb( Base_Reg, 0x11 ) ; + VS->V_Retrace_End = inb( Target_Reg ) ; + outb( Base_Reg, 0x12 ) ; + VS->V_Display_End = inb( Target_Reg ) ; + outb( Base_Reg, 0x13 ) ; + VS->Underline_Loc = inb( Target_Reg ) ; + outb( Base_Reg, 0x14 ) ; + VS->Offset = inb( Target_Reg ) ; + outb( Base_Reg, 0x15 ) ; + VS->V_Blank_Start = inb( Target_Reg ) ; + outb( Base_Reg, 0x16 ) ; + VS->V_Blank_End = inb( Target_Reg ) ; + outb( Base_Reg, 0x17 ) ; + VS->CRTC_Mode = inb( Target_Reg ) ; + outb( Base_Reg, 0x18 ) ; + VS->Line_Compare = inb( Target_Reg ) ; + /* Readjust Base Register */ + Base_Reg -= 0x4 ; + + /* Sequencer Registers 03C4 & 03C5 */ + /* VS->Seq_Addr_Reg = inb( 0x3C4 ) ; */ /* 03C4 -- SAME */ + outb( 0x3C4, 0x00 ) ; + VS->Seq_Reset = inb( 0x3C5 ) ; + outb( 0x3C4, 0x01 ) ; + VS->Clock_Mode = inb( 0x3C5 ) ; + outb( 0x3C4, 0x02 ) ; + VS->Mask_Map = inb( 0x3C5 ) ; + outb( 0x3C4, 0x03 ) ; + VS->Char_Map_Select = inb( 0x3C5 ) ; + outb( 0x3C4, 0x04 ) ; + VS->Memory_Mode = inb( 0x3C5 ) ; + + /* Graphics Registers 03CE & 03CF */ + /* VS->Graphics_Addr = inb( 0x3CE ) ; */ /* 03CE -- SAME */ + /* ??????? */ /* 03CF -- SAME */ + outb( 0x3CE, 0x00 ) ; + VS->Set_Reset = inb( 0x3CF ) ; + outb( 0x3CE, 0x01 ) ; + VS->Enb_Set_Reset = inb( 0x3CF ) ; + outb( 0x3CE, 0x02 ) ; + VS->Color_Compare = inb( 0x3CF ) ; + outb( 0x3CE, 0x03 ) ; + VS->Data_Rotate = inb( 0x3CF ) ; + outb( 0x3CE, 0x04 ) ; + VS->Read_Map_Select = inb( 0x3CF ) ; + outb( 0x3CE, 0x05 ) ; + VS->Graphics_Mode = inb( 0x3CF ) ; + outb( 0x3CE, 0x06 ) ; + VS->Miscellaneous = inb( 0x3CF ) ; + outb( 0x3CE, 0x07 ) ; + VS->Color_Dont_Care = inb( 0x3CF ) ; + outb( 0x3CE, 0x08 ) ; + VS->Bit_Mask = inb( 0x3CF ) ; /* Graphics_Addr == 08 */ + + /* Video DAC Registers 03CE & 03CF */ + VS->PEL_WR_Addr = inb( 0x3C8 ) ; /* 03C8 -- SAME */ + /* PEL_RD_Addr is WRITE-ONLY */ + VS->DAC_State = inb( 0x3C7 ) ; /* XXXX -- 03C7 */ + VS->PEL_Data_Reg = inb( 0x3C9 ) ; /* 03C9 -- SAME */ + VS->PEL_Mask_Reg = inb( 0x3C6 ) ; + + return ; + } ; + + void + restore_vga_state( VS ) + register struct vga_video_hardware_state * const VS ; + { + register IO_Address Base_Reg ; /* if mono == 0x3B0, if color == 3D0 */ + register IO_Address Target_Reg ; + + /* Setup I/O Base Address */ + Base_Reg = ( VS->Misc_Output_Reg & 1 ) ? 0x3D0 : 0x3B0 ; + + /* Sequencer Registers 03C4 & 03C5 */ + /* Do Hardware Syncronous RESET */ + SetVideoSequencer( Seq_ResetIndex, VS->Seq_Reset & 0xFD ) ; + SetVideoSequencer( Clock_ModeIndex, VS->Clock_Mode ) ; + SetVideoSequencer( Mask_MapIndex, VS->Mask_Map ) ; + SetVideoSequencer( Char_Map_SelectIndex, VS->Char_Map_Select ) ; + SetVideoSequencer( Memory_ModeIndex, VS->Memory_Mode ) ; + + /* Write General Registers */ + outb( 0x3C2, VS->Misc_Output_Reg ) ; + /* VS->Input_Status_0 & VS->Input_Status_1 are READ-ONLY */ + outb( Base_Reg + 0xA, VS->Feature_Control ) ; + outb( 0x3C3, VS->Video_Enable ) ; + + /* Attribute Registers */ + /* Initialize Flip-Flop */ + { register tmp = inb( Base_Reg + 0xA ) ; } + + /* Target_Reg Used As Scrap */ + for ( Target_Reg = 0 ; Target_Reg <= 0xF ; Target_Reg++ ) { + SetVideoAttribute( Target_Reg, VS->Palette[Target_Reg] ) ; + } + SetVideoAttribute( AttributeModeIndex, VS->Attr_Mode ) ; + SetVideoAttribute( OverScanColorIndex, VS->Overscan_Color ) ; + SetVideoAttribute( ColorPlaneEnableIndex, VS->Color_Plane_En ) ; + SetVideoAttribute( HorizPelPanIndex, VS->Horiz_PEL_Pan ) ; + SetVideoAttribute( ColorSelectIndex, VS->Color_Select ) ; + + /* Enable CRT Controller Registers 0-7 */ + outb( Target_Reg = ( Base_Reg += 0x4 ), 0x11 ) ; + outb( ++Target_Reg, 0x0C ) ; + /* Restore Crt Controller Registers 03?4 & 03?5 */ + outb( Base_Reg, 0x00 ) ; + outb( Target_Reg, VS->Horiz_Total ) ; + outb( Base_Reg, 0x01 ) ; + outb( Target_Reg, VS->Horiz_End ) ; + outb( Base_Reg, 0x02 ) ; + outb( Target_Reg, VS->H_Blank_Start ) ; + outb( Base_Reg, 0x03 ) ; + outb( Target_Reg, VS->H_Blank_End ) ; + outb( Base_Reg, 0x04 ) ; + outb( Target_Reg, VS->H_Retrace_Start ) ; + outb( Base_Reg, 0x05 ) ; + outb( Target_Reg, VS->H_Retrace_End ) ; + outb( Base_Reg, 0x06 ) ; + outb( Target_Reg, VS->Vert_Total ) ; + outb( Base_Reg, 0x07 ) ; + outb( Target_Reg, VS->Overflow ) ; + outb( Base_Reg, 0x08 ) ; + outb( Target_Reg, VS->Preset_Row_Scan ) ; + outb( Base_Reg, 0x09 ) ; + outb( Target_Reg, VS->Max_Scan_Line ) ; + outb( Base_Reg, 0x0A ) ; + outb( Target_Reg, VS->Cursor_Start ) ; + outb( Base_Reg, 0x0B ) ; + outb( Target_Reg, VS->Cursor_End ) ; + outb( Base_Reg, 0x0C ) ; + outb( Target_Reg, VS->Start_Addr_Hi ) ; + outb( Base_Reg, 0x0D ) ; + outb( Target_Reg, VS->Start_Addr_Lo ) ; + outb( Base_Reg, 0x0E ) ; + outb( Target_Reg, VS->Cursor_Loc_Hi ) ; + outb( Base_Reg, 0x0F ) ; + outb( Target_Reg, VS->Cursor_Loc_Lo ) ; + outb( Base_Reg, 0x10 ) ; + outb( Target_Reg, VS->V_Retrace_Start ) ; + outb( Base_Reg, 0x11 ) ; + outb( Target_Reg, VS->V_Retrace_End ) ; + outb( Base_Reg, 0x12 ) ; + outb( Target_Reg, VS->V_Display_End ) ; + outb( Base_Reg, 0x13 ) ; + outb( Target_Reg, VS->Underline_Loc ) ; + outb( Base_Reg, 0x14 ) ; + outb( Target_Reg, VS->Offset ) ; + outb( Base_Reg, 0x15 ) ; + outb( Target_Reg, VS->V_Blank_Start ) ; + outb( Base_Reg, 0x16 ) ; + outb( Target_Reg, VS->V_Blank_End ) ; + outb( Base_Reg, 0x17 ) ; + outb( Target_Reg, VS->CRTC_Mode ) ; + outb( Base_Reg, 0x18 ) ; + outb( Target_Reg, VS->Line_Compare ) ; + + /* Restore Graphics Registers 03CE & 03CF */ + SetVideoGraphics( Set_ResetIndex, VS->Set_Reset ) ; + SetVideoGraphics( Enb_Set_ResetIndex, VS->Enb_Set_Reset ) ; + SetVideoGraphics( Color_CompareIndex, VS->Color_Compare ) ; + SetVideoGraphics( Data_RotateIndex, VS->Data_Rotate ) ; + SetVideoGraphics( Read_Map_SelectIndex, VS->Read_Map_Select ) ; + SetVideoGraphics( Graphics_ModeIndex, VS->Graphics_Mode ) ; + SetVideoGraphics( MiscellaneousIndex, VS->Miscellaneous ) ; + SetVideoGraphics( Color_Dont_CareIndex, VS->Color_Dont_Care ) ; + SetVideoGraphics( Bit_MaskIndex, VS->Bit_Mask ) ; /* Graphics_Addr == 08 */ + + /* Restore ?? Video DAC Registers 03C7 & 03C8 */ + outb( 0x3C9, VS->PEL_Data_Reg ) ; /* 03C9 -- SAME */ + outb( 0x3C6, VS->PEL_Mask_Reg ) ; + + /* Re-Enable Hardware i.e. Reset Register */ + SetVideoSequencer( Seq_ResetIndex, VS->Seq_Reset | 0x03 ) ; + + return ; + } ; + + void + vgaSetColor( color, r, g, b ) + register unsigned long int color ; + register short r, b, g ; + { + outb( 0x3C8, color ) ; /* Point PEL Address Register To Color Entry */ + outb( 0x3C9, r >> 2 ) ; + outb( 0x3C9, g >> 2 ) ; + outb( 0x3C9, b >> 2 ) ; + + return ; + } + + void + save_dac( tablePtr ) + register DAC_TABLE tablePtr ; + { + register int i ; + register unsigned char *cptr ; + + outb( 0x3C7, 0x0 ) ; /* Point PEL Address Register To First Entry */ + for ( i = 768, cptr = (unsigned char *) tablePtr ; --i ; ) + *cptr++ = inb( 0x03C9 ) ; + return ; + } + + void + restore_dac( tablePtr ) + register DAC_TABLE tablePtr ; + { + register int i ; + register unsigned char *cptr ; + + outb( 0x3C8, 0x0 ) ; /* Point PEL Address Register To First Entry */ + for ( i = 768, cptr = (unsigned char *) tablePtr ; --i ; ) + outb( 0x03C9, *cptr++ ) ; + return ; + } + + /* + * Initialize the vga to 640 x 480, 16 of 64 colors @ a0000 + OR -- Initialize the vga to 720 x 540, 16 of 64 colors @ a0000 + */ + + void + set_graphics_mode( VS ) + register struct vga_video_hardware_state *VS ; + { + /* Setup I/O Base Address */ + /* Color 640 by 480 -- 16 Color + OR - Color 720 by 540 -- 16 Color */ + #define Color_Base_Reg ( 0x3D0 ) + + /* Sequencer Registers 03C4 & 03C5 */ + SetVideoSequencer( Seq_ResetIndex, 0x01 ) ; /* Syncronous RESET */ + SetVideoSequencer( Clock_ModeIndex, 0x01 ) ; + /* Make All Planes Writable */ + SetVideoSequencer( Mask_MapIndex, VGA_ALLPLANES ) ; + SetVideoSequencer( Char_Map_SelectIndex, 0x00 ) ; + SetVideoSequencer( Memory_ModeIndex, 0x06 ) ; + + /* Write General Registers */ + /* VS.Input_Status_0 & VS.Input_Status_1 are READ-ONLY */ + #ifndef VGA720 + outb( 0x3C2, /* VS.Misc_Output_Reg */ 0xE3 ) ; /* VS.Misc_Output_Reg */ + #else /* VGA720 */ + outb( 0x3C2, 0xE7 ) ; /* VS.Misc_Output_Reg */ /* XXX */ + #endif + outb( Color_Base_Reg + 0xA, VS->Feature_Control ) ; + outb( 0x3C3, /* VS.Video_Enable */ 0x1 ) ; + + /* Re-Enable Hardware i.e. Reset Register */ + outb( 0x3C4, 0x00 ) ; + outb( 0x3C5, /* VS.Seq_Reset */ 0x03 ) ; /* Enable Hardware Reset Register */ + + /* Attribute Registers */ + /* + INTS_OFF() ; + */ + /* Initialize Flip-Flop */ + { register tmp = inb( Color_Base_Reg + 0xA ) ; } + + /* Set Palette Register Value Equal To Palette Register Index Number */ + /* i.e. Palette is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F */ + { + register IO_Address Target_Reg ; + for ( Target_Reg = 0 ; Target_Reg <= 0xF ; Target_Reg++ ) { + SetVideoAttribute( Target_Reg, Target_Reg ) ; + } + } + /* Rest Of The Attribute Registers */ + /* Note: 0x20 is added to the index + * to Re-Enable Video Access To The Color Palette */ + /* VS.Attr_Mode - P4,P5 for color select */ + SetVideoAttribute( AttributeModeIndex, 0x81 ) ; + SetVideoAttribute( OverScanColorIndex, 0x00 ) ; + SetVideoAttribute( ColorPlaneEnableIndex, VGA_ALLPLANES ) ; + SetVideoAttribute( HorizPelPanIndex, 0x00 ) ; + SetVideoAttribute( ColorSelectIndex, 0x00 ) ; + + /* Enable CRT Controller Registers 0-7 */ + outb( 0x3D4, 0x11 ) ; + outb( 0x3D5, 0x0C ) ; + /* Set CRT Controller Registers 03?4 & 03?5 */ + outb( 0x3D4, 0x00 ) ; + #ifndef VGA720 + outb( 0x3D5, 95 ) ; /* VS.Horiz_Total */ + #else /* VGA720 */ + outb( 0x3D5, 105 ) ; /* VS.Horiz_Total */ /* XXX */ + #endif + outb( 0x3D4, 0x01 ) ; + #ifndef VGA720 + outb( 0x3D5, 79 ) ; /* VS.Horiz_End */ + #else /* VGA720 */ + outb( 0x3D5, 89 ) ; /* VS.Horiz_End */ /* XXX */ + #endif + outb( 0x3D4, 0x02 ) ; + #ifndef VGA720 + outb( 0x3D5, 0x50 ) ; /* VS.H_Blank_Start */ + #else /* VGA720 */ + outb( 0x3D5, 0x5A ) ; /* VS.H_Blank_Start */ /* XXX */ + #endif + outb( 0x3D4, 0x03 ) ; + #ifndef VGA720 + outb( 0x3D5, /* VS.H_Blank_End */ 0x82 ) ; + #else /* VGA720 */ + outb( 0x3D5, 0x8A ) ; /* VS.H_Blank_End */ /* XXX */ + #endif + outb( 0x3D4, 0x04 ) ; + #ifndef VGA720 + outb( 0x3D5, /* VS.H_Retrace_Start */ 0x54 ) ; + #else /* VGA720 */ + outb( 0x3D5, 0x5C ) ; /* VS.H_Retrace_Start */ /* XXX */ + #endif + outb( 0x3D4, 0x05 ) ; + #ifndef VGA720 + outb( 0x3D5, /* VS.H_Retrace_End */ 0x80 ) ; + #else /* VGA720 */ + outb( 0x3D5, 0x88 ) ; /* VS.H_Retrace_End */ + #endif + outb( 0x3D4, 0x06 ) ; + #ifndef VGA720 + outb( 0x3D5, /* VS.Vert_Total */ 0x0B ) ; + #else /* VGA720 */ + outb( 0x3D5, /* VS.Vert_Total */ 0x4F ) ; /* XXX */ + #endif + outb( 0x3D4, 0x07 ) ; + #ifndef VGA720 + outb( 0x3D5, /* VS.Overflow */ 0x3E ) ; + #else /* VGA720 */ + outb( 0x3D5, /* VS.Overflow */ 0xF0 ) ; /* XXX */ + #endif + outb( 0x3D4, 0x08 ) ; + outb( 0x3D5, /* VS.Preset_Row_Scan */ 0 ) ; + outb( 0x3D4, 0x09 ) ; + #ifndef VGA720 + outb( 0x3D5, /* VS.Max_Scan_Line */ 0x40 ) ; + #else /* VGA720 */ + outb( 0x3D5, /* VS.Max_Scan_Line */ 0x60 ) ; /* XXX */ + #endif + outb( 0x3D4, 0x0A ) ; + outb( 0x3D5, /* VS.Cursor_Start */ 0 ) ; + outb( 0x3D4, 0x0B ) ; + outb( 0x3D5, /* VS.Cursor_End */ 0 ) ; + outb( 0x3D4, 0x0C ) ; + outb( 0x3D5, /* VS.Start_Addr_Hi */ 0 ) ; + outb( 0x3D4, 0x0D ) ; + outb( 0x3D5, /* VS.Start_Addr_Lo */ 0 ) ; + outb( 0x3D4, 0x0E ) ; + outb( 0x3D5, /* VS.Cursor_Loc_Hi */ 0 ) ; + outb( 0x3D4, 0x0F ) ; + outb( 0x3D5, /* VS.Cursor_Loc_Lo */ 0 ) ; + outb( 0x3D4, 0x10 ) ; + #ifndef VGA720 + outb( 0x3D5, /* VS.V_Retrace_Start */ 234 ) ; + #else /* VGA720 */ + outb( 0x3D5, /* VS.V_Retrace_Start */ 32 ) ; /* XXX */ + #endif + outb( 0x3D4, 0x11 ) ; + outb( 0x3D5, /* VS.V_Retrace_End */ 0x8C ) ; + outb( 0x3D4, 0x12 ) ; + #ifndef VGA720 + outb( 0x3D5, /* VS.V_Display_End */ 223 ) ; + #else /* VGA720 */ + outb( 0x3D5, /* VS.V_Display_End */ 27 ) ; /* XXX */ + #endif + outb( 0x3D4, 0x13 ) ; + #ifndef VGA720 + outb( 0x3D5, /* VS.Underline_Loc */ 40 ) ; + #else /* VGA720 */ + outb( 0x3D5, /* VS.Offset */ 45 ) ; /* XXX */ + #endif + outb( 0x3D4, 0x14 ) ; + #ifndef VGA720 + outb( 0x3D5, /* VS.Offset */ 0 ) ; + #else /* VGA720 */ + outb( 0x3D5, /* VS.Underline_Loc */ 0 ) ; + #endif + outb( 0x3D4, 0x15 ) ; + #ifndef VGA720 + outb( 0x3D5, /* VS.V_Blank_Start */ 231 ) ; + #else /* VGA720 */ + outb( 0x3D5, /* VS.V_Blank_Start */ 35 ) ; /* XXX */ + #endif + outb( 0x3D4, 0x16 ) ; + #ifndef VGA720 + outb( 0x3D5, /* VS.V_Blank_End */ 4 ) ; + #else /* VGA720 */ + outb( 0x3D5, /* VS.V_Blank_End */ 2 ) ; + #endif + outb( 0x3D4, 0x17 ) ; + outb( 0x3D5, /* VS.CRTC_Mode */ 0xE3 ) ; + outb( 0x3D4, 0x18 ) ; + outb( 0x3D5, /* VS.Line_Compare */ 255 ) ; + + /* Set Graphics Registers 03CE & 03CF */ + SetVideoGraphics( Set_ResetIndex, 0x00 ) ; + SetVideoGraphics( Enb_Set_ResetIndex, 0x00 ) ; + SetVideoGraphics( Color_CompareIndex, 0x00 ) ; + SetVideoGraphics( Data_RotateIndex, 0x00 ) ; + SetVideoGraphics( Read_Map_SelectIndex, 0x00 ) ; + SetVideoGraphics( Graphics_ModeIndex, VGA_WRITE_MODE_2 ) ; + SetVideoGraphics( MiscellaneousIndex, 0x05 ) ; + SetVideoGraphics( Color_Dont_CareIndex, VGA_ALLPLANES ) ; + SetVideoGraphics( Bit_MaskIndex, 0xFF ) ; /* All Bits Writable */ + + /* Video DAC Registers 03C7 & 03C8 */ + outb( 0x3C9, VS->PEL_Data_Reg ) ; /* 03C9 -- SAME */ + outb( 0x3C6, VS->PEL_Mask_Reg ) ; + + return ; + } *** X11R4.ORIG/mit/server/ddx/xenix/trident/vgaReg.h Sun Jan 6 01:04:05 1991 --- X11R4/mit/server/ddx/xenix/trident/vgaReg.h Mon Oct 15 15:36:33 1990 *************** *** 0 **** --- 1,134 ---- + /* + * Copyright IBM Corporation 1987,1988,1989 + * + * All Rights Reserved + * + * Permission to use, copy, modify, and distribute this software and its + * documentation for any purpose and without fee is hereby granted, + * provided that the above copyright notice appear in all copies and that + * both that copyright notice and this permission notice appear in + * supporting documentation, and that the name of IBM not be + * used in advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * + * IBM DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING + * ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL + * IBM BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR + * ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, + * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, + * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + * + */ + /*********************************************************** + Copyright IBM Corporation 1987,1988 + + All Rights Reserved + + Permission to use, copy, modify, and distribute this software and its + documentation for any purpose and without fee is hereby granted, + provided that the above copyright notice appear in all copies and that + both that copyright notice and this permission notice appear in + supporting documentation, and that the name of IBM not be + used in advertising or publicity pertaining to distribution of the + software without specific, written prior permission. + + IBM DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING + ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL + IBM BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR + ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, + WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, + ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + SOFTWARE. + + ******************************************************************/ + + /* $Header: /andrew/X11/R3src/earlyRelease/server/ddx/ibm/vga/RCS/vgaReg.h,v 6.1 88/10/30 20:23:42 paul Exp $ */ + /* $Source: /andrew/X11/R3src/earlyRelease/server/ddx/ibm/vga/RCS/vgaReg.h,v $ */ + + #if !defined(lint) && !defined(LOCORE) && defined(RCS_HDRS) + static char *rcsidvga_reg = "$Header: /andrew/X11/R3src/earlyRelease/server/ddx/ibm/vga/RCS/vgaReg.h,v 6.1 88/10/30 20:23:42 paul Exp $"; + #endif + + #define SET_BYTE_REGISTER( ioport, value ) outb( ioport, value ) + #define SET_INDEX_REGISTER( ioport, value ) SET_BYTE_REGISTER( ioport, value ) + #define SET_DATA_REGISTER( ioport, value ) SET_BYTE_REGISTER( ioport, value ) + #if defined(RTIO) || defined(ATRIO) + #define SET_INDEXED_REGISTER( RegGroup, index, value ) \ + outw( RegGroup, ( ( index ) << 8 ) | ( value ) ) + #else + #if defined(PCIO) + #define SET_INDEXED_REGISTER( RegGroup, index, value ) \ + outw( RegGroup, ( ( value ) << 8 ) | ( index ) ) + #else + ******** ERROR ******** + #endif + #endif + + /* There is a jumper on the ega to change this to 0x200 instead !! */ + #define REGBASE 0x300 + + #define AttributeIndexRegister REGBASE + 0xC0 + #define AttributeDataWriteRegister REGBASE + 0xC0 + #define AttributeDataReadRegister REGBASE + 0xC1 + #define AttributeRegister AttributeIndexRegister + #define AttributeModeIndex 0x30 + #define OverScanColorIndex 0x31 + #define ColorPlaneEnableIndex 0x32 + #define HorizPelPanIndex 0x33 + #define ColorSelectIndex 0x34 + #define SetVideoAttributeIndex( index ) \ + SET_INDEX_REGISTER( AttributeIndexRegister, index ) + #define SetVideoAttribute( index, value ) \ + SetVideoAttributeIndex( index ) ; \ + SET_BYTE_REGISTER( AttributeDataWriteRegister, value ) + + /* Graphics Registers 03CE & 03CF */ + #define GraphicsIndexRegister REGBASE + 0xCE + #define GraphicsDataRegister REGBASE + 0xCF + #define GraphicsRegister GraphicsIndexRegister + #define Set_ResetIndex 0x00 + #define Enb_Set_ResetIndex 0x01 + #define Color_CompareIndex 0x02 + #define Data_RotateIndex 0x03 + #define Read_Map_SelectIndex 0x04 + #define Graphics_ModeIndex 0x05 + #define MiscellaneousIndex 0x06 + #define Color_Dont_CareIndex 0x07 + #define Bit_MaskIndex 0x08 + #define SetVideoGraphicsIndex( index ) \ + SET_INDEX_REGISTER( GraphicsIndexRegister, index ) + #define SetVideoGraphicsData( value ) \ + SET_INDEX_REGISTER( GraphicsDataRegister, value ) + #define SetVideoGraphics( index, value ) \ + SET_INDEXED_REGISTER( GraphicsRegister, index, value ) + + /* Sequencer Registers 03C4 & 03C5 */ + #define SequencerIndexRegister REGBASE + 0xC4 + #define SequencerDataRegister REGBASE + 0xC5 + #define SequencerRegister SequencerIndexRegister + #define Seq_ResetIndex 00 + #define Clock_ModeIndex 01 + #define Mask_MapIndex 02 + #define Char_Map_SelectIndex 03 + #define Memory_ModeIndex 04 + #define SetVideoSequencerIndex( index ) \ + SET_INDEX_REGISTER( SequencerIndexRegister, index ) + #define SetVideoSequencer( index, value ) \ + SET_INDEXED_REGISTER( SequencerRegister, index, value ) + + /* BIT CONSTANTS FOR THE VGA/EGA HARDWARE */ + /* for the Graphics' Data_Rotate Register */ + #define VGA_ROTATE_FUNC_SHIFT 3 + #define VGA_COPY_MODE ( 0 << VGA_ROTATE_FUNC_SHIFT ) /* 0x00 */ + #define VGA_AND_MODE ( 1 << VGA_ROTATE_FUNC_SHIFT ) /* 0x08 */ + #define VGA_OR_MODE ( 2 << VGA_ROTATE_FUNC_SHIFT ) /* 0x10 */ + #define VGA_XOR_MODE ( 3 << VGA_ROTATE_FUNC_SHIFT ) /* 0x18 */ + /* for the Graphics' Graphics_Mode Register */ + #define VGA_READ_MODE_SHIFT 3 + #define VGA_WRITE_MODE_0 0 + #define VGA_WRITE_MODE_1 1 + #define VGA_WRITE_MODE_2 2 + #define VGA_WRITE_MODE_3 3 + #define VGA_READ_MODE_0 ( 0 << VGA_READ_MODE_SHIFT ) + #define VGA_READ_MODE_1 ( 1 << VGA_READ_MODE_SHIFT ) *** X11R4.ORIG/mit/server/ddx/xenix/trident/vgaSave.h Sun Jan 6 01:04:07 1991 --- X11R4/mit/server/ddx/xenix/trident/vgaSave.h Mon Oct 15 15:36:33 1990 *************** *** 0 **** --- 1,140 ---- + /* + * Copyright IBM Corporation 1987,1988,1989 + * + * All Rights Reserved + * + * Permission to use, copy, modify, and distribute this software and its + * documentation for any purpose and without fee is hereby granted, + * provided that the above copyright notice appear in all copies and that + * both that copyright notice and this permission notice appear in + * supporting documentation, and that the name of IBM not be + * used in advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * + * IBM DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING + * ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL + * IBM BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR + * ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, + * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, + * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + * SOFTWARE. + * + */ + /*********************************************************** + Copyright IBM Corporation 1987,1988 + + All Rights Reserved + + Permission to use, copy, modify, and distribute this software and its + documentation for any purpose and without fee is hereby granted, + provided that the above copyright notice appear in all copies and that + both that copyright notice and this permission notice appear in + supporting documentation, and that the name of IBM not be + used in advertising or publicity pertaining to distribution of the + software without specific, written prior permission. + + IBM DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING + ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL + IBM BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR + ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, + WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, + ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS + SOFTWARE. + + ******************************************************************/ + /* $Header: /andrew/X11/r3src/earlyRelease/server/ddx/ibm/vga/RCS/vgaSave.h,v 6.2 88/11/24 00:35:06 paul Exp $ */ + /* $Source: /andrew/X11/r3src/earlyRelease/server/ddx/ibm/vga/RCS/vgaSave.h,v $ */ + + #if !defined(lint) && !defined(LOCORE) && defined(RCS_HDRS) + static char *rcsidvgaSave = "$Header: /andrew/X11/r3src/earlyRelease/server/ddx/ibm/vga/RCS/vgaSave.h,v 6.2 88/11/24 00:35:06 paul Exp $"; + #endif + + typedef unsigned char io86reg ; /* 8 bit hardware registers */ + typedef short int IO_Address ; /* 64K Intel-Style I/O space */ + + typedef unsigned char DAC_TABLE[768] ; + + struct vga_video_hardware_state { + /* Address locations READ -- WRITE */ + /* General Registers */ + io86reg Misc_Output_Reg ; /* 03CC -- 03C2 */ + io86reg Input_Status_0 ; /* 03C2 -- XXXX */ + io86reg Input_Status_1 ; /* 03?A -- XXXX */ + io86reg Feature_Control ; /* 03?C -- 03CA */ + io86reg Video_Enable ; /* 03C3 -- SAME */ + + /* Attribute Registers 03C0 & 03C1 */ + io86reg Attr_Addr_Reg ; /* 03C0 -- SAME */ + /* io86reg ??????? */ /* 03C0 -- SAME */ + io86reg Palette[16] ; /* Attr_Addr_Reg == 00 - 0F */ + io86reg Attr_Mode ; /* Attr_Addr_Reg == 10 */ + io86reg Overscan_Color ; /* Attr_Addr_Reg == 11 */ + io86reg Color_Plane_En ; /* Attr_Addr_Reg == 12 */ + io86reg Horiz_PEL_Pan ; /* Attr_Addr_Reg == 13 */ + io86reg Color_Select ; /* Attr_Addr_Reg == 14 */ + + /* Crt Controller Registers 03?4 & 03?5 */ + io86reg Index_Reg ; /* 03?4 -- SAME */ + /* io86reg ??????? */ /* 03?5 -- SAME */ + io86reg Horiz_Total ; /* Index_Reg == 00 */ + io86reg Horiz_End ; /* Index_Reg == 01 */ + io86reg H_Blank_Start ; /* Index_Reg == 02 */ + io86reg H_Blank_End ; /* Index_Reg == 03 */ + io86reg H_Retrace_Start ; /* Index_Reg == 04 */ + io86reg H_Retrace_End ; /* Index_Reg == 05 */ + io86reg Vert_Total ; /* Index_Reg == 06 */ + io86reg Overflow ; /* Index_Reg == 07 */ + io86reg Preset_Row_Scan ; /* Index_Reg == 08 */ + io86reg Max_Scan_Line ; /* Index_Reg == 09 */ + io86reg Cursor_Start ; /* Index_Reg == 0A */ + io86reg Cursor_End ; /* Index_Reg == 0B */ + io86reg Start_Addr_Hi ; /* Index_Reg == 0C */ + io86reg Start_Addr_Lo ; /* Index_Reg == 0D */ + io86reg Cursor_Loc_Hi ; /* Index_Reg == 0E */ + io86reg Cursor_Loc_Lo ; /* Index_Reg == 0F */ + io86reg V_Retrace_Start ; /* Index_Reg == 10 */ + io86reg V_Retrace_End ; /* Index_Reg == 11 */ + io86reg V_Display_End ; /* Index_Reg == 12 */ + io86reg Underline_Loc ; /* Index_Reg == 13 */ + io86reg Offset ; /* Index_Reg == 14 */ + io86reg V_Blank_Start ; /* Index_Reg == 15 */ + io86reg V_Blank_End ; /* Index_Reg == 16 */ + io86reg CRTC_Mode ; /* Index_Reg == 17 */ + io86reg Line_Compare ; /* Index_Reg == 18 */ + + /* Sequencer Registers 03C4 & 03C5 */ + io86reg Seq_Addr_Reg ; /* 03C4 -- SAME */ + /* io86reg ??????? */ /* 03?5 -- SAME */ + io86reg Seq_Reset ; /* Seq_Addr_Reg == 00 */ + io86reg Clock_Mode ; /* Seq_Addr_Reg == 01 */ + io86reg Mask_Map ; /* Seq_Addr_Reg == 02 */ + io86reg Char_Map_Select ; /* Seq_Addr_Reg == 03 */ + io86reg Memory_Mode ; /* Seq_Addr_Reg == 04 */ + + /* Graphics Registers 03CE & 03CF */ + io86reg Graphics_Addr ; /* 03CE -- SAME */ + /* io86reg ??????? */ /* 03CF -- SAME */ + io86reg Set_Reset ; /* Graphics_Addr == 00 */ + io86reg Enb_Set_Reset ; /* Graphics_Addr == 01 */ + io86reg Color_Compare ; /* Graphics_Addr == 02 */ + io86reg Data_Rotate ; /* Graphics_Addr == 03 */ + io86reg Read_Map_Select ; /* Graphics_Addr == 04 */ + io86reg Graphics_Mode ; /* Graphics_Addr == 05 */ + io86reg Miscellaneous ; /* Graphics_Addr == 06 */ + io86reg Color_Dont_Care ; /* Graphics_Addr == 07 */ + io86reg Bit_Mask ; /* Graphics_Addr == 08 */ + + /* Video DAC Registers 03CE & 03CF */ + io86reg PEL_WR_Addr ; /* 03C8 -- SAME */ + io86reg PEL_RD_Addr ; /* XXXX -- 03C7 */ + io86reg DAC_State ; /* XXXX -- 03C7 */ + io86reg PEL_Data_Reg ; /* 03C9 -- SAME */ + io86reg PEL_Mask_Reg ; /* 03C6 -- SAME */ + } ; + + /* Global Flag for Virtual Screen Saves */ + extern int vgaDisabled ; + + #define PhysicalVgaAccessDisabled 0x1 + #define VirtualVgaHardwareOpenPending 0x2 + #define VirtualVgaHardwareClosePending 0x4 *** X11R4.ORIG/mit/server/ddx/xenix/trident/vgaTrident.c Sun Jan 6 01:04:12 1991 --- X11R4/mit/server/ddx/xenix/trident/vgaTrident.c Mon Dec 3 00:12:20 1990 *************** *** 0 **** --- 1,318 ---- + #include + #include + #include "vgaSave.h" + + struct port_io_arg vga_port; + + extern xenixVGAFd; + + unsigned char inb( port ) + unsigned int port; + { + vga_port.args[0].dir = IN_ON_PORT; + vga_port.args[0].port = port; + ioctl(xenixVGAFd, VGAIO, &vga_port); + return(vga_port.args[0].data); + } + + void outb( port, data ) + unsigned int port; + unsigned char data; + { + vga_port.args[0].dir = OUT_ON_PORT; + vga_port.args[0].port = port; + vga_port.args[0].data = data; + ioctl(xenixVGAFd, VGAIO, &vga_port); + } + + void outw( port, word ) + unsigned int port; + unsigned int word; + { + outb(port, (unsigned char)(word >> 8)); + outb(port+1, (unsigned char)(word)); + } + + vga_color_init(fb_addr,bg_color,fg_color,fb_size) + char *fb_addr; + int bg_color, fg_color; + long int fb_size; + { + char *fb_ptr; + + /* set write mode 3 for writing the background */ + /* Graphics Controller: 0x3cf, Address port 0x3ce */ + outb(0x3ce, 0x05); /* Mode Register */ + outb(0x3cf, 0x0b); /* xxxx1011 */ + outb(0x3ce, 0x01); /* Enable Set/Reset Register */ + outb(0x3cf, 0x0f); /* type b of write mode 0 */ + outb(0x3ce, 0x08); /* Bit Mask Register */ + outb(0x3cf, 0xff); /* Don't mask anything: 0xff */ + outb(0x3ce, 0x03); /* Data Rotate/Function Select Register */ + outb(0x3cf, 0x00); /* pixel replace with no rotation */ + + /* set registers for read mode 1 */ + outb(0x3ce, 0x07); /* Color Don't Care */ + outb(0x3cf, bg_color ^ fg_color); /* only where bg and fg differs */ + outb(0x3ce, 0x02); /* Color Compare */ + outb(0x3cf, fg_color); + + /* unlock all bit planes */ + outb(0x3c4, 0x02); + outb(0x3c5, 0xf); + + /* initialize screen with background color */ + outb(0x3ce, 0x00); /* Set/Reset Register */ + outb(0x3cf, bg_color); + for (fb_ptr=fb_addr; fb_size; fb_ptr++, fb_size--) + *fb_ptr = 0xff; + + /* lock all bit planes except where bg and fg differs */ + outb(0x3c4, 0x02); + outb(0x3c5, bg_color ^ fg_color); + + /* set write mode 0, read mode 1 for pixel read write */ + /* Graphics Controller: 0x3cf, Address port 0x3ce */ + outb(0x3ce, 0x05); /* Mode Register */ + outb(0x3cf, 0x08); /* xxxx1000 */ + outb(0x3ce, 0x01); /* Enable Set/Reset Register */ + outb(0x3cf, 0x00); /* type b of write mode 0 */ + outb(0x3ce, 0x08); /* Bit Mask Register */ + outb(0x3cf, 0xff); /* Don't mask anything: 0xff */ + outb(0x3ce, 0x03); /* Data Rotate/Function Select Register */ + outb(0x3cf, 0x00); /* pixel replace with no rotation */ + } + + void + trident_vga1( VS ) + register struct vga_video_hardware_state *VS; + { + } + + void + trident_vga2( VS ) + register struct vga_video_hardware_state *VS; + { + /* Miscellaneous Output Register */ + VS->Misc_Output_Reg = 0x2B; + + /* Attribute Registers 00 - 14 */ + VS->Palette[0] = 0x00; + VS->Palette[1] = 0x01; + VS->Palette[2] = 0x02; + VS->Palette[3] = 0x03; + VS->Palette[4] = 0x04; + VS->Palette[5] = 0x05; + VS->Palette[6] = 0x14; + VS->Palette[7] = 0x07; + VS->Palette[8] = 0x38; + VS->Palette[9] = 0x39; + VS->Palette[10] = 0x3A; + VS->Palette[11] = 0x3B; + VS->Palette[12] = 0x3C; + VS->Palette[13] = 0x3D; + VS->Palette[14] = 0x3E; + VS->Palette[15] = 0x3F; + VS->Attr_Mode = 0x01; + VS->Overscan_Color = 0x00; + VS->Color_Plane_En = 0x0F; + VS->Horiz_PEL_Pan = 0x00; + VS->Color_Select = 0x00; + + /* CRT Controller Registers 00 - 18 */ + VS->Horiz_Total = 0x99; + VS->Horiz_End = 0x63; + VS->H_Blank_Start = 0x64; + VS->H_Blank_End = 0x1C; + VS->H_Retrace_Start = 0x74; + VS->H_Retrace_End = 0x10; + VS->Vert_Total = 0x7F; + VS->Overflow = 0xF0; + VS->Preset_Row_Scan = 0x00; + VS->Max_Scan_Line = 0x60; + VS->Cursor_Start = 0x00; + VS->Cursor_End = 0x00; + VS->Start_Addr_Hi = 0x00; + VS->Start_Addr_Lo = 0x00; + VS->Cursor_Loc_Hi = 0x00; + VS->Cursor_Loc_Lo = 0x00; + VS->V_Retrace_Start = 0x5E; + VS->V_Retrace_End = 0x8E; + VS->V_Display_End = 0x57; + VS->Underline_Loc = 0x32; + VS->Offset = 0x00; + VS->V_Blank_Start = 0x58; + VS->V_Blank_End = 0x7F; + VS->CRTC_Mode = 0xE3; + VS->Line_Compare = 0xFF; + + /* Sequencer Registers 00 - 04 */ + VS->Seq_Reset = 0x03; + VS->Clock_Mode = 0x01; + VS->Mask_Map = 0x0F; + VS->Char_Map_Select = 0x00; + VS->Memory_Mode = 0x06; + + /* Graphics Registers 00 - 08 */ + VS->Set_Reset = 0x00; + VS->Enb_Set_Reset = 0x00; + VS->Color_Compare = 0x00; + VS->Data_Rotate = 0x00; + VS->Read_Map_Select = 0x00; + VS->Graphics_Mode = 0x00; + VS->Miscellaneous = 0x05; + VS->Color_Dont_Care = 0x0F; + VS->Bit_Mask = 0xFF; + } + + void + trident_vga3( VS ) + register struct vga_video_hardware_state *VS; + { + /* Miscellaneous Output Register */ + VS->Misc_Output_Reg = 0x2B; + + /* Attribute Registers 00 - 14 */ + VS->Palette[0] = 0x00; + VS->Palette[1] = 0x01; + VS->Palette[2] = 0x02; + VS->Palette[3] = 0x03; + VS->Palette[4] = 0x04; + VS->Palette[5] = 0x05; + VS->Palette[6] = 0x14; + VS->Palette[7] = 0x07; + VS->Palette[8] = 0x38; + VS->Palette[9] = 0x39; + VS->Palette[10] = 0x3A; + VS->Palette[11] = 0x3B; + VS->Palette[12] = 0x3C; + VS->Palette[13] = 0x3D; + VS->Palette[14] = 0x3E; + VS->Palette[15] = 0x3F; + VS->Attr_Mode = 0x01; + VS->Overscan_Color = 0x00; + VS->Color_Plane_En = 0x0F; + VS->Horiz_PEL_Pan = 0x00; + VS->Color_Select = 0x00; + + /* CRT Controller Registers 00 - 18 */ + VS->Horiz_Total = 0x99; + VS->Horiz_End = 0x7F; + VS->H_Blank_Start = 0x81; + VS->H_Blank_End = 0x1B; + VS->H_Retrace_Start = 0x83; + VS->H_Retrace_End = 0x1B; + VS->Vert_Total = 0x9D; + VS->Overflow = 0xf0/*0x1F*/; + VS->Preset_Row_Scan = 0x00; + VS->Max_Scan_Line = 0x60/*0x00*/; + VS->Cursor_Start = 0x00; + VS->Cursor_End = 0x00; + VS->Start_Addr_Hi = 0x00; + VS->Start_Addr_Lo = 0x00; + VS->Cursor_Loc_Hi = 0x00; + VS->Cursor_Loc_Lo = 0x00; + VS->V_Retrace_Start = 0x74/*0x84*/; + VS->V_Retrace_End = 0x10/*0x8C*/; + VS->V_Display_End = 0x57/*0x7F*/; + VS->Underline_Loc = 0x40/*0x80*/; + VS->Offset = 0x00; + VS->V_Blank_Start = 0x84; + VS->V_Blank_End = 0x98; + VS->CRTC_Mode = 0xE3; + VS->Line_Compare = 0xFF; + + /* Sequencer Registers 00 - 04 */ + VS->Seq_Reset = 0x03; + VS->Clock_Mode = 0x01; + VS->Mask_Map = 0x0F; + VS->Char_Map_Select = 0x00; + VS->Memory_Mode = 0x06; + + /* Graphics Registers 00 - 08 */ + VS->Set_Reset = 0x00; + VS->Enb_Set_Reset = 0x00; + VS->Color_Compare = 0x00; + VS->Data_Rotate = 0x00; + VS->Read_Map_Select = 0x00; + VS->Graphics_Mode = 0x00; + VS->Miscellaneous = 0x05; + VS->Color_Dont_Care = 0x0F; + VS->Bit_Mask = 0xFF; + } + + void + trident_vga4( VS ) + register struct vga_video_hardware_state *VS; + { + /* Miscellaneous Output Register */ + VS->Misc_Output_Reg = 0x2B; + + /* Attribute Registers 00 - 14 */ + VS->Palette[0] = 0x00; + VS->Palette[1] = 0x01; + VS->Palette[2] = 0x02; + VS->Palette[3] = 0x03; + VS->Palette[4] = 0x04; + VS->Palette[5] = 0x05; + VS->Palette[6] = 0x14; + VS->Palette[7] = 0x07; + VS->Palette[8] = 0x38; + VS->Palette[9] = 0x39; + VS->Palette[10] = 0x3A; + VS->Palette[11] = 0x3B; + VS->Palette[12] = 0x3C; + VS->Palette[13] = 0x3D; + VS->Palette[14] = 0x3E; + VS->Palette[15] = 0x3F; + VS->Attr_Mode = 0x01; + VS->Overscan_Color = 0x00; + VS->Color_Plane_En = 0x0F; + VS->Horiz_PEL_Pan = 0x00; + VS->Color_Select = 0x00; + + /* CRT Controller Registers 00 - 18 */ + VS->Horiz_Total = 0x99; + VS->Horiz_End = 0x7F; + VS->H_Blank_Start = 0x81; + VS->H_Blank_End = 0x1B; + VS->H_Retrace_Start = 0x83; + VS->H_Retrace_End = 0x1B; + VS->Vert_Total = 0x9D; + VS->Overflow = 0x1F; + VS->Preset_Row_Scan = 0x00; + VS->Max_Scan_Line = 0x00; + VS->Cursor_Start = 0x00; + VS->Cursor_End = 0x00; + VS->Start_Addr_Hi = 0x00; + VS->Start_Addr_Lo = 0x00; + VS->Cursor_Loc_Hi = 0x00; + VS->Cursor_Loc_Lo = 0x00; + VS->V_Retrace_Start = 0x84; + VS->V_Retrace_End = 0x8C; + VS->V_Display_End = 0x7F; + VS->Underline_Loc = 0x80; + VS->Offset = 0x00; + VS->V_Blank_Start = 0x84; + VS->V_Blank_End = 0x98; + VS->CRTC_Mode = 0xE3; + VS->Line_Compare = 0xFF; + + /* Sequencer Registers 00 - 04 */ + VS->Seq_Reset = 0x03; + VS->Clock_Mode = 0x01; + VS->Mask_Map = 0x0F; + VS->Char_Map_Select = 0x00; + VS->Memory_Mode = 0x06; + + /* Graphics Registers 00 - 08 */ + VS->Set_Reset = 0x00; + VS->Enb_Set_Reset = 0x00; + VS->Color_Compare = 0x00; + VS->Data_Rotate = 0x00; + VS->Read_Map_Select = 0x00; + VS->Graphics_Mode = 0x00; + VS->Miscellaneous = 0x05; + VS->Color_Dont_Care = 0x0F; + VS->Bit_Mask = 0xFF; + }