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From: mash@mips.COM (John Mashey)
Newsgroups: comp.arch
Subject: Re: R4000
Message-ID: <45791@mips.mips.COM>
Date: 11 Feb 91 21:25:07 GMT
References: <45448@mips.mips.COM> <1991Feb1.223326.18683@watdragon.waterloo.edu> <45525@mips.mips.COM> <obgVpm200VpeQ4VmIa@andrew.cmu.edu>
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In article <obgVpm200VpeQ4VmIa@andrew.cmu.edu> mh2f+@andrew.cmu.edu (Mark Hahn) writes:
>isn't MIPS's "superpiplining" just the common trick 
>of sticking in a clock doubler?
No, it's more complicated than that.  The typical bottleneck is the
latency of the caches.  From 5-stage R3000 pipeline, we went to
an 8-stage pipeline for the R4000, not 10.  The cache-access phases
got split into several phases; some others didn't because they
weren't bottlenecks.  The "superpipelined" comes from issuing
2 instructions in the cache-latency period, by issuing 1 every half-cycle,
rather than in 2-way superscalar, where you fetch and issue 2 in parallel.
>
>would anyone care to comment on the argument
>that "the amount of instruction-level parallelism 
>that is available limits the benefit" of superscalar?
>It seems like I saw simulation papers claiming
>superscalar speedups of 2-3x.  besides, wouldn't
>MIPS still have to resolve the same dependencies,
>and thus be subject to the same limits?  
>(assuming the r4000 isn't just a clock speedup.)
As a simple example why they are different, suppose you have
a chunk of code that looks like:
	add	a,b,c	a = b+c
	sub	a,a,d	a = a-d
A typical 2-way superscalar would have a stall on the sub, because
it needs data from the first, IF the 2 instructions were fetched together,
and IF the compilers couldn't rearrange things.
A superpipelined design would not have that stall,
if the pipeline managed to get the ALU stage to be a half-cycle
(as the R4000).  
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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